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PDF A25LQ080 Data sheet ( Hoja de datos )
| Número de pieza | A25LQ080 | |
| Descripción | Dual/Quad-I/O Serial Flash Memory | |
| Fabricantes | AMIC | |
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A25LQ080 Series
8Mbit, 3V Suspend/Resume, Dual/Quad-I/O Serial Flash Memory
with 100MHz Uniform 4KB Sectors
Document Title
8Mbit, 3V Suspend/Resume, Dual/Quad-I/O Serial Flash Memory with 100MHz Uniform 4KB
Sectors
Revision History
Rev. No. History
1.0 Final version issue
Issue Date
April 1, 2016
Remark
Final
(April, 2016, Version 1.0)
AMIC Technology Corp.
AMIC reserves the right to change products and specifications discussed herein without notice.
1 page  
SPI MODES
These devices can be driven by a microcontroller with its SPI
peripheral running in either of the two following modes:
– CPOL=0, CPHA=0
– CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising
edge of Serial Clock (C), and output data is available from the
A25LQ080 Series
falling edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 1,
is the clock polarity when the bus master is in Stand-by mode
and not transferring data:
– C remains at 0 for (CPOL=0, CPHA=0) Æ Mode 0
– C remains at 1 for (CPOL=1, CPHA=1) Æ Mode 3
Figure 1. SPI Modes Supported
CPOL CPHA
Mode 0 0
0C
Mode 3 1
1C
DIO
DO
MSB
MSB
(April, 2016, Version 1.0)
4 AMIC Technology Corp.
5 Page 
INSTRUCTIONS
All instructions, addresses and data are shifted in and out of
the device, most significant bit first.
Serial Data Input(s) IO0 (IO1, IO2, IO3) is (are) sampled on the
first rising edge of Serial Clock (C) after Chip Select ( S ) is
driven Low. Then, the one-byte instruction code must be
shifted in to the device, most significant bit first, on Serial Data
Input(s) IO0 (IO1, IO2, IO3), each bit being latched on the rising
edges of Serial Clock (C).
The instruction set is listed in Table 3.
Every instruction sequence starts with a one-byte instruction
code. Depending on the instruction, this might be followed by
address bytes, or by data bytes, or by dummy bytes (don’t
care), or by a combination or none.
In the case of a Read Data Bytes (READ), Read Data Bytes at
Higher Speed (Fast_Read), Read Data Bytes at Higher Speed
by Dual Output (FAST_READ_DUAL_OUTPUT), Read Data
Bytes at Higher Speed by Dual Input and Dual Output
(FAST_READ_DUAL_INPUT_OUTPUT) , Read Data Bytes at
Higher Speed by Quad Output (FAST_READ_QUAD
_OUTPUT), Read Data Bytes at Higher Speed by Quad Input
and Quad Output (FAST_READ_QUAD_INPUT_OUTPUT),
Read OTP (ROTP), Read Identification (RDID), Read
Electronic Manufacturer and Device Identification (REMS),
A25LQ080 Series
Read Status Register (RDSR) or Release from Deep
Power-down, Read Device Identification and Read Electronic
Signature (RES) instruction, the shifted-in instruction se-
quence is followed by a data-out sequence. Chip Select ( S )
can be driven High after any bit of the data-out sequence is
being shifted out.
In the case of a Page Program (PP), Program OTP (POTP),
Dual Input Fast Program (DIFP), Quad Input Fast Program
(QIFP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE),
Write Status Register (WRSR), Write Enable (WREN), Write
Disable (WRDI) or Deep Power-down (DP) instruction, Chip
Select ( S ) must be driven High exactly at a byte boundary,
otherwise the instruction is rejected, and is not executed. That
is, Chip Select ( S ) must driven High when the number of
clock pulses after Chip Select ( S ) being driven Low is an
exact multiple of eight.
All attempts to access the memory array during a Write Status
Register cycle, Program cycle or Erase cycle are ignored, and
the internal Write Status Register cycle, Program cycle or
Erase cycle continues unaffected.
(April, 2016, Version 1.0)
10 AMIC Technology Corp.
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet A25LQ080.PDF ] | |
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