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PDF UJA1066TW Data sheet ( Hoja de datos )
| Número de pieza | UJA1066TW | |
| Descripción | High-speed CAN fail-safe system basis chip | |
| Fabricantes | NXP Semiconductors | |
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UJA1066
High-speed CAN fail-safe system basis chip
Rev. 03 — 17 March 2010
Product data sheet
1. General description
The UJA1066 fail-safe System Basis Chip (SBC) replaces basic discrete components
which are common in every Electronic Control Unit (ECU) with a Controller Area Network
(CAN) interface. The fail-safe SBC supports all networking applications that control
various power and sensor peripherals by using high-speed CAN as the main network
interface. The fail-safe SBC contains the following integrated devices:
• High-speed CAN transceiver, interoperable and downward compatible with CAN
transceiver TJA1041 and TJA1041A, and compatible with the ISO 11898-2 standard
and the ISO 11898-5 standard (in preparation)
• Advanced independent watchdog
• Dedicated voltage regulators for microcontroller and CAN transceiver
• Serial peripheral interface (full duplex)
• Local wake-up input port
• Inhibit/limp-home output port
In addition to the advantages of integrating these common ECU functions in a single
package, the fail-safe SBC offers an intelligent combination of system-specific functions
such as:
• Advanced low-power concept
• Safe and controlled system start-up behavior
• Advanced fail-safe system behavior that prevents any conceivable deadlock
• Detailed status reporting on system and subsystem levels
The UJA1066 is designed to be used in combination with a microcontroller that
incorporates a CAN controller. The fail-safe SBC ensures that the microcontroller is
always started up in a defined manner. In failure situations, the fail-safe SBC will maintain
microcontroller functionality for as long as possible to provide a full monitoring and
software-driven fallback operation.
The UJA1066 is designed for 14 V single power supply architectures and for 14 V and
42 V dual power supply architectures.
1 page  
NXP Semiconductors
5. Pinning information
5.1 Pinning
UJA1066
High-speed CAN fail-safe system basis chip
n.c. 1
n.c. 2
TEST1 3
V1 4
TEST2 5
RSTN 6
INTN 7
EN 8
SDI 9
SDO 10
SCK 11
SCS 12
TXDC 13
RXDC 14
n.c. 15
TEST3 16
Fig 2. Pin configuration
UJA1066TW
32 BAT42
31 SENSE
30 V3
29 SYSINH
28 n.c.
27 BAT14
26 TEST5
25 TEST4
24 SPLIT
23 GND
22 CANL
21 CANH
20 V2
19 n.c.
18 WAKE
17 INH/LIMP
015aaa016
5.2 Pin description
UJA1066_2
Product data sheet
Table 2.
Symbol
n.c.
n.c.
i.c.
V1
i.c.
RSTN
INTN
EN
SDI
SDO
SCK
SCS
TXDC
RXDC
n.c.
TEST
Pin description
Pin Description
1 not connected
2 not connected
3 internally connected; must be left open in the application
4 voltage regulator output for the microcontroller (3.3 V or 5 V depending on the
SBC version)
5 internally connected; must be left open in the application
6 reset output to microcontroller (active LOW; will detect clamping situations)
7 interrupt output to microcontroller (active LOW; open-drain; wire-AND this pin to
other ECU interrupt outputs)
8 enable output (active HIGH; push-pull; LOW with every reset/watchdog
overflow)
9 SPI data input
10 SPI data output (floating when pin SCS is HIGH)
11 SPI clock input
12 SPI chip select input (active LOW)
13 CAN transmit data input (LOW when dominant; HIGH when recessive)
14 CAN receive data output (LOW when dominant; HIGH when recessive)
15 not connected
16 test pin (should be connected to ground in the application)
All information provided in this document is subject to legal disclaimers.
Rev. 03 — 17 March 2010
© NXP B.V. 2010. All rights reserved.
5 of 70
5 Page 
NXP Semiconductors
UJA1066
High-speed CAN fail-safe system basis chip
• Cyclic wake-up by the watchdog via an interrupt signal to the microcontroller (the
microcontroller is triggered periodically and checked for the correct response)
• Cyclic wake-up by the watchdog via a reset signal (a reset is performed periodically;
the SBC provides information about the reset source to allow different start
sequences after reset)
• Wake-up by activity on the CAN-bus via an interrupt signal to the microcontroller
• Wake-up by bus activity on the CAN-bus via a reset signal
• Wake-up by increasing the microcontroller supply current without a reset signal
(where a stable supply is needed for the microcontroller RAM contents to remain valid
and wake-up from an external application not connected to the SBC)
• Wake-up by increasing the microcontroller supply current with a reset signal
• Wake-up due to a falling edge at pin WAKE forcing an interrupt to the microcontroller
• Wake-up due to a falling edge at pin WAKE forcing a reset signal
6.2.6 Sleep mode
In Sleep mode the microcontroller power supply (V1) and the INH/LIMP-controlled
external supplies are switched off entirely, resulting in minimum system power
consumption. In this mode, the watchdog runs in Time-out mode or is completely off.
Entering Sleep mode results in an immediate LOW level on pin RSTN, stopping all
microcontroller operations. The INH/LIMP output is floating in parallel and pin V1 is
disabled. Only pin SYSINH can remain active to support the V2 voltage supply (if bit V2C
is set; see Table 12). V3 can also be ON, OFF or in Cyclic mode to supply external
wake-up switches.
If the watchdog is not disabled by software, it will continue to run and will force a system
reset once the programmed watchdog period has expired. The SBC then enters Start-up
mode and pin V1 becomes active again. This behavior can be used to implement cyclic
wake-up from Sleep mode.
Depending on the application, the following operations can be selected from Sleep mode:
• Cyclic wake-up by the watchdog (only in Time-out mode); a reset is performed
periodically, the SBC provides information about the reset source to allow the
microcontroller to choose between different start up sequences after reset
• Wake-up by activity on the CAN-bus or falling edge on pin WAKE
• An overload on V3, only if V3 is in a cyclic or a continuously ON mode
6.2.7 Flash mode
Flash mode can only be entered from Normal mode by entering a specific Flash mode
entry sequence. This fail-safe control sequence comprises three consecutive write
accesses to the Mode register, within the legal windows of the watchdog, using the
operating mode codes 111, 001 and 111 respectively. Once this sequence has been
received, the SBC will enter Start-up mode and perform a system reset using the related
reset source information (bits RSS[3:0] = 0110).
UJA1066_2
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 03 — 17 March 2010
© NXP B.V. 2010. All rights reserved.
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