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PDF 24FC1026 Data sheet ( Hoja de datos )
| Número de pieza | 24FC1026 | |
| Descripción | EEPROM | |
| Fabricantes | Microchip | |
| Logotipo |  |
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24AA1026/24LC1026/24FC1026
1024K I2C Serial EEPROM
Device Selection Table
Part
Number
VCC
Range
Max. Clock Temp.
Frequency Ranges
24AA1026
24LC1026
24FC1026
1.7V-5.5V
2.5V-5.5V
1.8V-5.5V
400 kHz(1)
400 kHz(2)
1 MHz(3)
I
I, E
I
Note 1: 100 kHz for VCC < 2.5V
2: 100 kHz for VCC < 4.5V (E-temp)
3: 400 kHz for VCC < 2.5V
Features
• Low-Power CMOS Technology:
- Read current 450 µA, maximum
- Standby current 5 µA, maximum
• 2-Wire Serial Interface, I2C Compatible
• Cascadable up to Four Devices
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to Eliminate Ground Bounce
• 100 kHz and 400 kHz Clock Compatibility
• 1 MHz Clock for FC Versions
• Page Write Time 3 ms, typical
• Self-Timed Erase/Write Cycle
• 128-Byte Page Write Buffer
• Hardware Write-Protect
• Electrostatic Discharge (ESD) Protection >4000V
• More than One Million Erase/Write Cycles
• Data Retention >200 Years
• Factory Programming Available
• Packages Include 8-lead PDIP, SOIC and SOIJ
• RoHS Compliant
• Temperature Ranges:
- Industrial (I): -40C to +85C
- Automotive (E): -40C to +125C
Description
The Microchip Technology Incorporated
24AA1026/24LC1026/24FC1026 (24XX1026*) is a
128K x 8 (1024 Kbit) Serial Electrically Erasable
PROM, capable of operation across a broad voltage
range (1.7V to 5.5V).
It has been developed for advanced, low-power
applications such as personal communications or data
acquisition. This device has both byte write and page
write capability of up to 128 bytes of data.
This device is capable of both random and sequential
reads. Reads may be sequential within address
boundaries 0000h to FFFFh and 10000h to 1FFFFh.
Functional address lines allow up to four devices on the
same data bus. This allows for up to 4 Mbits total
system EEPROM memory. This device is available in
the standard 8-pin PDIP, SOIC and SOIJ packages.
Package Type
8-Lead PDIP
8-Lead SOIC/SOIJ
NC 1
A1 2
A2 3
VSS 4
8 VCC NC
7 WP A1
6 SCL A2
5 SDA VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
Block Diagram
A1A2 WP
HV Generator
I/O
Control
Logic
Memory
Control
Logic
I/O SCL
SDA
VCC
VSS
XDEC
EEPROM
Array
Page Latches
YDEC
Sense AMP
R/W Control
*24XX1026 is used in this document as a generic part
number for the 24AA1026/24LC1026/24FC1026
devices.
2011-2015 Microchip Technology Inc.
DS20002270E-page 1
1 page  
24AA1026/24LC1026/24FC1026
FIGURE 1-1:
BUS TIMING DATA
5
2
SCL
SDA
IN
SDA
OUT
7
6
15
3
89
13
(protected)
WP
(unprotected)
D3
4
10
14
11 12
2011-2015 Microchip Technology Inc.
DS20002270E-page 5
5 Page 
24AA1026/24LC1026/24FC1026
7.0 ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete. (This feature can be used to maximize bus
throughput.) Once the Stop condition for a Write
command has been issued from the master, the device
initiates the internally timed write cycle. ACK polling
can be initiated immediately. This involves the master
sending a Start condition, followed by the control byte
for a Write command (R/W = 0). If the device is still
busy with the write cycle, then no ACK will be returned.
If no ACK is returned, then the Start bit and control byte
must be resent. If the cycle is complete, then the device
will return the ACK and the master can then proceed
with the next Read or Write command. See Figure 7-1
for flow diagram.
Note:
Care must be taken when polling the
24XX1026. The control byte that was
used to initiate the write needs to match
the control byte used for polling.
FIGURE 7-1:
ACKNOWLEDGE
POLLING FLOW
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
Yes
Next
Operation
No
2011-2015 Microchip Technology Inc.
DS20002270E-page 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 24FC1026.PDF ] | |
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