PDF BLUENRG-1 Data sheet ( Hoja de datos )

Número de pieza	BLUENRG-1
Descripción	Bluetooth low energy wireless system-on-chip
Fabricantes	STMicroelectronics
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BlueNRG-1 Bluetooth® low energy wireless system-on-chip Datasheet - production data WLCSP34 QFN32 Features  Bluetooth specification compliant master, slave and multiple roles simultaneously, single-mode Bluetooth low energy system- on-chip  Operating supply voltage: from 1.7 to 3.6 V  Integrated linear regulator and DC-DC step- down converter  Operating temperature range: -40 °C to 105 °C  High performance, ultra-low power Cortex- M0 32-bit based architecture core  Programmable 160 KB Flash  24 KB RAM with retention (two 12 KB banks)  1 x UART interface  1 x SPI interface  2 x I2C interface  14 or 15 GPIO  2 x multifunction timer  10-bit ADC  Watchdog & RTC  DMA controller  PDM stream processor  16 or 32 MHz crystal oscillator  32 kHz crystal oscillator  32 kHz ring oscillator  Battery voltage monitor and temperature sensor  Up to +8 dBm available output power (at antenna connector)  Excellent RF link budget (up to 96 dB)  Accurate RSSI to allow power control  8.2 mA maximum TX current (@ 0 dBm, 3.0 V)  Down to 1 µA current consumption with active BLE stack (sleep mode)  Compliant with the following radio frequency regulations: ETSI EN 300 328, EN 300 440, FCC CFR47 Part 15, ARIB STD-T66  Pre-programmed bootloader via UART  QFN32, WCSP34 package option  Dedicated wettable flank QFN package for automotive grade qualification Applications  Automotive product  Watches  Fitness, wellness and sports  Consumer medical  Security/proximity  Remote control  Home and industrial automation  Assisted living  Mobile phone peripherals  Lighting  PC peripherals Table 1: Device summary table Order code Package Packing BLUENRG-132 QFN32 (5 x 5 mm) Tape and reel BLUENRG-134 WLCSP34 Tape and reel BLUENRG-132Y QFN32 (5 x 5 mm) Automotive grade Level Tape and reel June 2016 DocID028866 Rev 1 This is information on a product in full production. 1/173 www.st.com 1 page BlueNRG-1 List of tables List of tables Table 1: Device summary table ..................................................................................................................1 Table 2: Interrupt vectors ..........................................................................................................................15 Table 3: Relationship between BlueNRG-1 states and functional blocks ................................................17 Table 4: SYSTEM_CTRL registers...........................................................................................................18 Table 5: SYSTEM_CTRL - WKP_IO_IS register description: address offset SYSTEM_CTRL_BASE_ADDR+0x00 ......................................................................................................18 Table 6: SYSTEM_CTRL - WKP_IO_IE register description: address offset SYSTEM_CTRL_BASE_ADDR+0x04 ......................................................................................................19 Table 7: SYSTEM_CTRL - CTRL register description: address offset SYSTEM_CTRL_BASE_ADDR+0x08 ......................................................................................................19 Table 8: AHBUPCONV registers ..............................................................................................................19 Table 9: BLUE_CTRL registers ................................................................................................................19 Table 10: CKGEN_SOC registers ............................................................................................................23 Table 11: CKGEN_SOC - CONTROL register description: address offset CKGEN_SOC_BASE_ADDR+0x00 .........................................................................................................23 Table 12: CKGEN_SOC - REASON_RST register description: address offset CKGEN_SOC_BASE_ADDR+0x08 .........................................................................................................24 Table 13: CKGEN_SOC - DIE_ID register description: address offset CKGEN_SOC_BASE_ADDR+0x1C .........................................................................................................24 Table 14: CKGEN_SOC - CLOCK_EN register description: address offset CKGEN_SOC_BASE_ADDR+0x20 .........................................................................................................24 Table 15: CKGEN_SOC - DMA_CONFIG register description: address offset CKGEN_SOC_BASE_ADDR+0x24 .........................................................................................................25 Table 16: CKGEN_BLE registers .............................................................................................................25 Table 17: CKGEN_BLE - REASON_RST register description: address offset CKGEN_BLE_BASE_ADDR+0x08 ..........................................................................................................25 Table 18: CKGEN_BLE - CLK32K_COUNT register description: address offset CKGEN_BLE_BASE_ADDR+0x0C ..........................................................................................................26 Table 19: CKGEN_BLE - CLK32K_PERIOD register description: address offset CKGEN_BLE_BASE_ADDR+0x10 ..........................................................................................................26 Table 20: CKGEN_BLE - CLK32K_FREQ register description: address offset CKGEN_BLE_BASE_ADDR+0x14 ..........................................................................................................26 Table 21: CKGEN_BLE - CLK32K_IT register description: address offset CKGEN_BLE_BASE_ADDR+0x18 ..........................................................................................................26 Table 22: ADC channels ...........................................................................................................................27 Table 23: ADC data rate ...........................................................................................................................28 Table 24: ADC data rate with microphone mode......................................................................................28 Table 25: ADC registers............................................................................................................................30 Table 26: ADC - CTRL register description: address offset ADC_BASE_ADDR+0x00...........................30 Table 27: ADC - CONF register description: address offset ADC_BASE_ADDR+0x04 ..........................31 Table 28: ADC - IRQSTAT register description: address offset ADC_BASE_ADDR+0x08.....................32 Table 29: ADC - IRQMASK register description: address offset ADC_BASE_ADDR+0x0C ...................33 Table 30: ADC - DATA_CONV register description: address offset ADC_BASE_ADDR+0x14 ..............33 Table 31: ADC - OFFSET register description: address offset ADC_BASE_ADDR+0x18 ......................33 Table 32: ADC - SR_REG register description: address offset ADC_BASE_ADDR+0x20 .....................33 Table 33: ADC - THRESHOLD_HI register description: address offset ADC_BASE_ADDR+0x24 ........34 Table 34: ADC - THRESHOLD_LO register description: address offset ADC_BASE_ADDR+0x28 .......34 Table 35: Programmable data width and endian behavior (when bits PINC = MINC = 1) .......................37 Table 36: DMA interrupt requests .............................................................................................................40 Table 37: DMA registers ...........................................................................................................................41 Table 38: DMA - ISR register description: address offset DMA_BASE_ADDR+0x00 .............................41 Table 39: DMA - IFCR register description: address offset DMA_BASE_ADDR+0x04 ...........................45 Table 40: DMA_CHx registers ..................................................................................................................47 DocID028866 Rev 1 5/173 5 Page BlueNRG-1 Description 1 Description The BlueNRG-1 is a very low power Bluetooth low energy (BLE) single-mode system-on- chip, compliant with Bluetooth specification. The BlueNRG-1 extends the features of award-winning BlueNRG network processor, enabling the usage of the embedded Cortex M0 for running the user application code. The BlueNRG-1 includes 160 KB of programming Flash memory, 24 KB of static RAM memory with retention (two 12 KB banks) and SPI, UART, I2C standard communication interface peripherals. It also features multifunction timers, watchdog, RTC and DMA controller. An ADC is available for interfacing with analog sensors, and for reading the measurement of the integrated battery monitor. A digital filter is available for processing a PDM stream. The BlueNRG-1 offers the same excellent RF performance of the BlueNRG radio, and the integrated high efficiency DC/DC converter keeps the same ultra-low power characteristics, but the BlueNRG-1 improves the BlueNRG sleep mode current consumption allowing a further increase in the battery lifetime of the applications. Figure 1: BlueNRG-1 architecture block diagram DocID028866 Rev 1 11/173 11 Page

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Número de pieza	Descripción	Fabricantes
BLUENRG-1	Bluetooth low energy wireless system-on-chip	STMicroelectronics
BLUENRG-132	Bluetooth low energy wireless system-on-chip	STMicroelectronics
BLUENRG-132Y	Bluetooth low energy wireless system-on-chip	STMicroelectronics
BLUENRG-134	Bluetooth low energy wireless system-on-chip	STMicroelectronics

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