파트넘버.co.kr 74HC190 데이터시트 PDF


74HC190 반도체 회로 부품 판매점

4 BIT SYNCHRONOUS UP/DOWN COUNTERS



SGS-THOMSON 로고
SGS-THOMSON
74HC190 데이터시트, 핀배열, 회로
M54/M74HC190
M54/M74HC191
4 BIT SYNCHRONOUS UP/DOWN COUNTERS
. HIGH SPEED
fMAX = 48 MHz (TYP.) AT VCC = 5 V
. LOW POWER DISSIPATION
ICC = 4 µA (MAX.) AT TA = 25 °C
. HIGH NOISE IMMUNITY
VNIH = VNIL = 28 % VCC (MIN.)
. OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
. SYMMETRICAL OUTPUT IMPEDANCE
IOH= IOL = 4 mA (MIN.)
. BALANCED PROPAGATION DELAYS
tPLH = tPHL
. WIDE OPERATING VOLTAGE RANGE
VCC (OPR) = 2 V TO 6 V
. PIN AND FUNCTION COMPATIBLE
WITH 54/74LS190/191
B1R
(Plastic Package)
F1R
(Ceramic Package)
M 1R
(Micro Package)
C1R
(Chip Carrier)
ORDER CODES :
M54HCXXXF1R M74HCXXXM1R
M74HCXXXB1R M74HCXXXC1R
PIN CONNECTIONS (top view)
DESCRIPTION
The M54/74HC190/191 are high speed CMOS 4-BIT
SYNCHRONOUS UP/DOWN COUNTERS fabri-
cated in silicon gate C2MOS technology.
They have the same high speed performance of
LSTTL combined with true CMOS low power con-
sumption.
State changes of the counter are synchronous with
the LOW-to-HIGH transition of the Clock Pulse input.
An asynchronous parallel load input overrides count-
ing and loads the data present on the DATA inputs into
the flip-flops, which makes it possible to use the cir-
cuits as programmable counters. A countenable input
serves as the carry/borrow input in multi-stage
counters. Control input, Down/Up, determines
whether a circuit counts up or down. A MAX/MIN out-
put and a Ripple Clock output provide overflow/under-
flow indication and make possible a variety of
methods for generating carry/borrow signals in multi-
stage counter applications.
All inputs are equipped with protection circuits against
static discharge and transient excess voltage.
NC =
No Internal
Connection
October 1992
1/14


74HC190 데이터시트, 핀배열, 회로
M54/M74HC190/191
INPUT AND OUTPUT EQUIVALENT CIRCUIT
IEC LOGIC SYMBOL (HC190)
PIN DESCRIPTION
PIN No
3, 2, 6, 7
4
5
11
12
13
14
15, 1, 10, 9
8
16
SYMBOL NAME AND FUNCTION
QA to QD Flip-Flop Outputs
ENABLE Count Enable Input
(Active LOW)
U/D Parallel Data Input
LOAD Load Input (Active LOW)
MA/MI OUT Terminal Count Output
RC Ripple Clock Output
(Active LOW)
CLOCK
Cloack Input (LOW to
HIGH, Edge-triggered)
DA to DD Data Inputs
GND
Ground (0V)
VCC Positive Supply Voltage
IEC LOGIC SYMBOL (HC191)
TRUTH TABLE
INPUTS
LOAD ENABLE
D/U
CLOCK
QA
L X X Xa
HLL
H LH
HHX
HXX
X: Don’t Care
a - d: The level of steady state inputs at inputs a through D respectively
OUTPUS
QB QC
bc
UP COUNT
DOWN COUNT
NO CHANGE
NO CHANGE
QD
d
FUNCTION
PRESET DATA
UP COUNT
DOWN COUNT
NO COUNT
NO COUNT
2/14




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