NP179N04TUK 반도체 회로 부품 판매점
N-channel Power MOS FET
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 Renesas |
Preliminary Data Sheet
NP179N04TUK
40 V – 180 A – N-channel Power MOS FET
Application: Automotive
R07DS1248EJ0100
Rev.1.00
Feb 12, 2015
Description
The NP179N04TUK is N-channel MOS Field Effect Transistors designed for high current switching applications.
Features
• Super low on-state resistance
RDS(on) = 1.25 mΩ MAX. (VGS = 10 V, ID = 90 A)
• Low Ciss
Ciss = 8900 pF TYP. (VDS = 25 V)
• Designed for automotive application and AEC-Q101 qualified
Ordering Information
Part No.
NP179N04TUK-E1-AY *1
NP179N04TUK-E2-AY *1
Lead Plating
Pure Sn (Tin)
Packing
Tape 800 p/reel
Taping (E1 type)
Taping (E2 type)
Note: *1 Pb-free (This product does not contain Pb in the external electrode)
Package
TO-263-7pin
Absolute Maximum Ratings (TA = 25°C)
Item
Symbol
Ratings
Drain to Source Voltage (VGS = 0 V)
Gate to Source Voltage (VDS = 0 V)
Drain Current (DC) (TC = 25°C)
Drain Current (pulse) *1
VDSS
VGSS
ID(DC)
ID(pulse)
40
±20
±180
±720
Total Power Dissipation (TC = 25°C)
Total Power Dissipation (TA = 25°C) *2
PT1
PT2
288
1.8
Channel Temperature
Tch 175
Storage Temperature
Repetitive Avalanche Current *3
Repetitive Avalanche Energy *3
Tstg –55 to +175
IAR 66
EAR 435
Notes: *1 TC = 25°C, PW ≤ 10 μs, Duty Cycle ≤ 1%
*2 Mounted on glass epoxy substrate of 40 mm × 40 mm × 1.6 mmt with 4% Copper area (35 μm)
*3 RG = 25 Ω, VGS = 20 V → 0 V
Unit
V
V
A
A
W
W
°C
°C
A
mJ
Thermal Resistance
Channel to Case Thermal Resistance
Channel to Ambient Thermal Resistance
Rth(ch-C)
Rth(ch-A)
0.52 °C/W
83.3 °C/W
R07DS1248EJ0100 Rev.1.00
Feb 12, 2015
Page 1 of 6
NP179N04TUK
Preliminary
Electrical Characteristics (TA = 25°C)
Item
Zero Gate Voltage Drain Current
Gate Leakage Current
Gate to Source Threshold Voltage
Forward Transfer Admittance *1
Drain to Source On-state Resistance *1
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
Total Gate Charge
Gate to Source Charge
Gate to Drain Charge
Body Diode Forward Voltage *1
Reverse Recovery Time
Reverse Recovery Charge
Note: *1 Pulsed test
Symbol
IDSS
IGSS
VGS(th)
| yfs |
RDS(on)
Ciss
Coss
Crss
td(on)
tr
td(off)
tf
QG
QGS
QGD
VF(S-D)
trr
Qrr
MIN.
—
—
2.0
65
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TYP.
—
—
3.0
130
1.05
8900
1200
440
33
12
110
16
160
42
42
0.9
63
100
MAX.
1
±100
4.0
—
1.25
13350
1800
800
80
30
220
40
240
—
—
1.5
—
—
Unit
μA
nA
V
S
mΩ
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
V
ns
nC
Test Conditions
VDS = 40 V, VGS = 0 V
VGS = ±20 V, VDS = 0 V
VDS = VGS, ID = 250 μA
VDS = 5 V, ID = 90 A
VGS = 10 V, ID = 90 A
VDS = 25 V
VGS = 0 V
f = 1 MHz
VDD = 20 V, ID = 90 A
VGS = 10 V
RG = 0 Ω
VDD = 32 V
VGS = 10 V
ID = 180 A
IF = 180 A, VGS = 0 V
IF = 180 A, VGS = 0 V
di/dt = 100 A/μs
TEST CIRCUIT 1 AVALANCHE CAPABILITY
D.U.T.
RG = 25 Ω
PG.
VGS = 20 → 0 V
50 Ω
L
VDD
BVDSS
ID
VDD
IAS
VDS
Starting Tch
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
IG = 2 mA
PG. 50 Ω
RL
VDD
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
PG. RG
VGS
0
τ
τ = 1 μs
Duty Cycle ≤ 1%
RL
VGS
VGS
Wave Form
10%
0
VDD
VDS
90%
VDS
VDS
Wave Form
0
td(on)
VGS 90%
90%
10% 10%
tr td(off)
tf
ton toff
R07DS1248EJ0100 Rev.1.00
Feb 12, 2015
Page 2 of 6
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