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PDF 5P49EE802 Data sheet ( Hoja de datos )
| Número de pieza | 5P49EE802 | |
| Descripción | Low-power Clock Generator | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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VersaClock® Low-power Clock Generator
5P49EE802
DATASHEET
Description
The 5P49EE802 is a programmable clock generator intended
for low power, battery operated consumer applications. There
are four internal PLLs, each individually programmable,
allowing for up to eight different output frequencies. The
frequencies are generated from a single reference clock. The
reference clock can come from either a TCXO or fundamental
mode crystal. An additional 32kHz crystal oscillator is
available to provide a real time clock or non-critical
performance MHz processor clock.
The 5P49EE802 can be programmed through the use of the
I2C interfaces. The programming interface enables the device
to be programmed when it is in normal operation or what is
commonly known as in system programmable. An internal
EEPROM allows the user to save and restore the
configuration of the device without having to reprogram it on
power-up.
Each of the four PLLs has an 8-bit reference divider and a
11-bit feedback divider. This allows the user to generate four
unique non-integer-related frequencies. The PLL loop
bandwidth is programmable to allow the user to tailor the PLL
response to the application. For instance, the user can tune
the PLL parameters to minimize jitter generation or to
maximize jitter attenuation. Spread spectrum generation is
supported on one of the PLLs.
Spread spectrum generation is supported on one of the PLLs.
The device is specifically designed to work with display
applications to ensure that the spread profile remains
consistent for each HSYNC in order to reduce ROW noise. It
also may operate in standard spread spectrum mode.
There are total seven 8-bit output dividers. Outputs are
LVCMOS. The outputs are connected to the PLLs via the
switch matrix. The switch matrix allows the user to route the
PLL outputs to any output bank. This feature can be used to
simplify and optimize the board layout. In addition, each
output's slew rate and enable/disable function can be
programmed.
Target Applications
• Smart Mobile Handset
• Personal Navigation Device (PND)
• Camcorder
• DSC
• Portable Game Console
• Personal Media Player
Features
• Four internal PLLs
• Internal non-volatile EEPROM
• Internal I2C EEPROM master interface
• FAST (400kHz) mode I2C serial interfaces
• Input Frequencies
– TCXO: 10 MHz to 40 MHz
– Crystal: 8 MHz to 30 MHz
– RTC Crystal: 32.768 kHz
• Output Frequency Ranges: kHz to 120 MHz
• Each PLL has an 8-bit reference divider and a 11-bit
feedback-divider
• 8-bit output-divider blocks
• One of the PLLs support Spread Spectrum generation
capable of configuration to pixel rate, with adjustable
modulation rate and amplitude to support video clock with
no visible artifacts
• I/O Standards:
– Outputs - 1.8V/2.5V/3.3 V LVTTL/ LVCMOS
– 3 independent adjustable VDDO groups
• Programmable Slew Rate Control
• Programmable Loop Bandwidth Settings
• Programmable output inversion to reduce bimodal jitter
• Individual output enable/disable
• Power-down/Sleep mode
– 10A max in power down mode
– 32kHz clock output active sleep mode
– 100A max in sleep mode
• 1.8V VDD Core Voltage
• Available in 28 pin 4x4mm QFN packages
• -40 to +85°C Industrial Temp operation
5P49EE802 REVISION P 04/01/16
1
©2016 Integrated Device Technology, Inc.
1 page  
PLL Features and Descriptions
5P49EE802 DATASHEET
D VCO
M XDIV
PLLA
PLLB
PLLC
PLLD
Ref-Divider
(D) Values
1 - 255
1 - 255
1 - 255
1 - 255
PLL Block Diagram
Feedback Feedback (M)
Pre-Divider
Values
(XDIV) Values
1 or 4
6 - 2047
4 6 - 2047
1 or 8 bit divide
6 - 2047
1 or 4
6 - 2047
Programmable
Loop Bandwidth
Yes
Yes
Yes
Yes
Spread Spectrum
Generation Capability
No
Yes
No
No
Crystal Input (XIN/REF)
The crystal oscillators should be fundamental mode quartz
crystals; overtone crystals are not suitable. Crystal frequency
should be specified for parallel resonance with 50 maximum
equivalent series resonance. 0
ONXTALB=0 bit needs to be set for XIN/REF.
Crystal Load Capacitors
The device crystal connections should include pads for small
capacitors from X1 to ground and from X2 to ground. These
capacitors are used to adjust the stray capacitance of the
board to match the nominally required crystal load
capacitance. Because load capacitance can only be
increased in this trimming process, it is important to keep stray
capacitance to a minimum by using very short PCB traces
(and no vias) between the crystal and device. Crystal
capacitors must be connected from each of the pins X1 and
X2 to ground.
Reference Pre-Divider, Reference Divider,
Feedback-Divider and Post-Divider
Each PLL incorporates an 8-bit reference-scaler and a 11-bit
feedback divider which allows the user to generate four
unique non-integer-related frequencies. PLLA and PLLD each
have a feedback pre-divider that provides additional
multiplication for kHz reference clock applications. Each
output divider supports 8-bit post-divider. The following
equation governs how the output frequency is calculated.
( )FOUT = FIN *
XDIV*M
D (Eq. 2)
ODIV
Where FIN is the reference frequency, XDIV is the feedback
pre-divider value, M is the feedback-divider value, D is the
reference divider value, ODIV is the total post-divider value,
and FOUT is the resulting output frequency. Programming any
of the dividers may cause glitches on the outputs.
The crystal capacitors are internal to the device and have an
effective value of 4pF.
REVISION P 04/01/16
5 VERSACLOCK® LOW-POWER CLOCK GENERATOR
5 Page 
5P49EE802 DATASHEET
Progread
Note: If the expected read command is not from the next higher register to the previous read or write command, then
set a known “read” register address prior to a read operation by issuing the following command:
Prior to Progread Command Set Register Address
The user can ignore the STOP condition above and use a repeated START condition instead, straight after the slave
acknowledgement bit (i.e., followed by the Progread command):
S Address R/W ACK ID Byte ACK Data_1 ACK Data_2 ACK Data_last NACK P
7-bits
1 1-bit 8-bits 1-bit 8-bits 1-bit 8-bits 1-bit 8-bits
1-bit
Progread Command Frame
Progsave
Note:
PROGWRITE is for writing to the 5P49EE802 registers.
PROGREAD is for reading the 5P49EE802 registers.
PROGSAVE is for saving all the contents of the 5P49EE802
registers to the EEPROM.
PROGRESTORE is for loading the entire EEPROM contents
to the 5P49EE802 registers.
Progrestore
During PROGRESTORE, outputs will be turned off to ensure
that no improper voltage levels are experienced before
initialization.
REVISION P 04/01/16
11 VERSACLOCK® LOW-POWER CLOCK GENERATOR
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet 5P49EE802.PDF ] | |
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