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ON Semiconductor |
NB3V60113G
1.8 V Programmable
OmniClock Generator
with Single Ended (LVCMOS) and Differential
(LVDS/HCSL) Outputs
The NB3V60113G, which is a member of the OmniClock family, is
a one−time programmable (OTP), low power PLL−based clock
generator that supports any output frequency from 8 kHz to 200 MHz.
The device accepts fundamental mode parallel resonant crystal or a
single ended (LVCMOS) reference clock as input. It generates either
three single ended (LVCMOS) outputs, or one single ended output and
one differential (LVDS/HCSL) output. The output signals can be
modulated using the spread spectrum feature of the PLL
(programmable spread spectrum type, deviation and rate) for
applications demanding low electromagnetic interference (EMI).
Using the PLL bypass mode, it is possible to get a copy of the input
clock on any or all of the outputs. The device can be powered down
using the Power Down pin (PD#). It is possible to program the internal
input crystal load capacitance and the output drive current provided by
the device. The device also has automatic gain control (crystal power
limiting) circuitry which avoids the device overdriving the external
crystal.
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WDFN8
CASE 511AT
MARKING DIAGRAM
1
V0MG
G
V0 = Specific Device Code
M = Date Code
G = Pb−Free Device
(Note: Microdot may be in either location)
Features
• Member of the OmniClock Family of Programmable Clock
Generators
• Operating Power Supply: 1.8 V ± 0.1 V
• I/O Standards
♦ Inputs: LVCMOS, Fundamental Mode Crystal
♦ Outputs: LVCMOS
♦ Outputs: LVDS and HCSL
• 3 Programmable Single Ended (LVCMOS) Outputs
from 8 kHz to 200 MHz
• 1 Programmable Differential Clock Output up to
200 MHz
• Input Frequency Range
♦ Crystal: 3 MHz to 50 MHz
♦ Reference Clock: 3 MHz to 200 MHz
• Configurable Spread Spectrum Frequency Modulation
Parameters (Type, Deviation, Rate)
• Programmable Internal Crystal Load Capacitors
• Programmable Output Drive Current for Single Ended
Outputs
ORDERING INFORMATION
See detailed ordering and shipping information on page 19 of
this data sheet.
• Power Saving mode through Power Down Pin
• Programmable PLL Bypass Mode
• Programmable Output Inversion
• Programming and Evaluation Kit for Field
Programming and Quick Evaluation
• Temperature Range −40°C to 85°C
• Packaged in 8−Pin WDFN
• These are Pb−Free Devices
Typical Applications
• eBooks and Media Players
• Smart Wearables, Portable Medical and Industrial
Equipment
• Set Top Boxes, Printers, Digital Cameras and
Camcorders
© Semiconductor Components Industries, LLC, 2016
January, 2016 − Rev. 2
1
Publication Order Number:
NB3V60113G/D
NB3V60113G
BLOCK DIAGRAM
VDD PD#
XIN/CLKIN
Crystal
XOUT
Crystal/Clock Control
Clock Buffer/
Crystal
Oscillator and
AGC
PLL Block
Phase
Detector
Configuration
Memory
Frequency
and SS
Charge
Pump
VCO
Feedback
Divider
Output control
Output
Divider
Output
Divider
CMOS/
Diff
buffer
CMOS /
Diff
buffer
Output
Divider
CMOS
buffer
PLL Bypass Mode
GND
Notes:
1. CLK0 and CLK1 can be configured to be one of LVDS or HCSL output, or two single−ended LVCMOS outputs.
2. Dotted lines are the programmable control signals to internal IC blocks.
3. PD# has internal pull down resistor.
Figure 1. Simplified Block Diagram
PIN FUNCTION DESCRIPTION
CLK0
CLK1
CLK2
XIN/CLKIN 1
XOUT 2
PD# 3
GND 4
NB3V60113G
8 CLK2
7 VDD
6 CLK1
5 CLK0
Figure 2. Pin Connections (Top View) – WDFN8
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2
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