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ADV3225 반도체 회로 부품 판매점

16 x 8 Analog Crosspoint Switch



Analog Devices 로고
Analog Devices
ADV3225 데이터시트, 핀배열, 회로
Data Sheet
FEATURES
16 × 8 high speed, nonblocking switch array
Pinout and functionally equivalent to the AD8110/AD8111
Drop-in compatible with the ADV3228/ADV3229 8 × 8 array
Complete solution
Buffered inputs
Programmable high impedance outputs
8 output amplifiers, G = +1 (ADV3224), G = +2 (ADV3225)
Drives 150 Ω loads
Operates on ±5 V supplies
Low power: 0.5 W
Excellent ac performance
−3 dB bandwidth
200 mV p-p: 1200 MHz (ADV3224), 900 MHz (ADV3225)
2 V p-p: 750 MHz (ADV3224), 850 MHz (ADV3225)
0.5 dB flatness (2 V p-p)
250 MHz (ADV3224), 235 MHz (ADV3225)
Slew rate: 2500 V/μs
Serial or parallel programming of switch array
72-lead LFCSP (10 mm × 10 mm)
APPLICATIONS
Routing of high speed signals including
Video (NTSC, PAL, S, SECAM, YUV, RGB)
Compressed video (MPEG, wavelet)
3-level digital video (HDB3)
Data communications
Telecommunications
GENERAL DESCRIPTION
The ADV3224/ADV3225 are high speed 16 × 8 analog crosspoint
switch matrices. They offer a −3 dB signal bandwidth of greater
than 750 MHz and a high slew rate of greater than 2500 V/μs.
The ADV3224/ADV3225 include eight independent output
buffers that can be placed into a high impedance state for
paralleling crosspoint outputs to prevent off channels from
loading the output bus. The ADV3224 has a gain of +1 and the
ADV3225 has a gain of +2, and they both operate on voltage
750 MHz, 16 × 8
Analog Crosspoint Switch
ADV3224/ADV3225
CLK
DATAIN
UPDATE
CE
RESET
FUNCTIONAL BLOCK DIAGRAM
SER/PAR D0 D1 D2 D3 D4
A0
A1
A2
40-BIT SHIFT REGISTER
WITH 4-BIT
PARALLEL LOADING
DATAOUT
40
PARALLEL LATCH
40
DECODE
8 × 5:16 DECODERS
SET INDIVIDUAL
OR RESET ALL
OUTPUTS TO OFF
8
ADV3224/
ADV3225
OUTPUT
128
BUFFER
G = +1,
G = +2
SWITCH
MATRIX
Figure 1.
supplies of ±5 V. Channel switching is performed via a serial
digital control that can accommodate the daisy chaining of
several devices or via a parallel control to allow updating of an
individual output without reprogramming the entire array.
The ADV3224/ADV3225 are available in the 72-lead LFCSP
package over the extended industrial temperature range of
−40°C to +85°C.
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2010–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com


ADV3225 데이터시트, 핀배열, 회로
ADV3224/ADV3225
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics (Serial) .................................................. 5
Logic Levels ................................................................................... 5
Timing Characteristics (Parallel) ............................................... 6
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
Power Dissipation......................................................................... 7
ESD Caution.................................................................................. 7
REVISION HISTORY
1/16—Rev. A to Rev. B
Change to Maximum Potential Difference (DVCC − AVEE)
Parameter, Table 5............................................................................. 7
Updated Outline Dimensions ....................................................... 24
12/10—Rev. 0 to Rev. A
Changes to Ordering Guide .......................................................... 24
11/10—Revision 0: Initial Version
Data Sheet
Pin Configuration and Function Descriptions..............................8
Truth Table and Logic Diagram ............................................... 10
Typical Performance Characteristics ........................................... 11
Circuit Diagrams ............................................................................ 20
Theory of Operation ...................................................................... 21
Applications Information .............................................................. 22
Serial Programming ................................................................... 22
Parallel Programming................................................................ 22
Power-On Reset.......................................................................... 23
Gain Selection............................................................................. 23
Creating Larger Crosspoint Arrays.......................................... 23
Outline Dimensions ....................................................................... 24
Ordering Guide .......................................................................... 24
Rev. B | Page 2 of 24




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