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ADM1260 반도체 회로 부품 판매점

Super Sequencer



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Analog Devices
ADM1260 데이터시트, 핀배열, 회로
Data Sheet
Super Sequencer with Interchip Bus and
Nonvolatile Fault Recording
ADM1260
FEATURES
Complete supervisory and sequencing solution for up to
10 supplies per device
Interchip bus (ICB) simplifies multidevice connections and
sequencing system operation
Supports up to 4 devices
16 event deep black box nonvolatile fault recording
10 supply fault detectors enable supervision of supplies
<0.5% accuracy at all voltages at 25°C
<1.0% accuracy across all voltages and temperatures
5 selectable input attenuators allow supervision of supplies
14.4 V on VH and 6.0 V on VP1 to VP4 (VPx)
5 dual function inputs: VX1 to VX5 (VXx)
High impedance input to supply fault detector with
thresholds between 0.573 V and 1.375 V
General-purpose logic input
10 programmable driver outputs: PDO1 to PDO10 (PDOx)
Open-collector with an external pull-up resistor
Push/pull output, driven to VDDCAP or VPx
Open-collector with weak pull-up to VDDCAP or VPx
Internally charge pumped high drive for use with external
N-FET (PDO1 to PDO6 only)
Sequencing engine (SE) implements state machine control of
the PDOx outputs
State changes conditional on input events
Enables complex control of boards
Power-up and power-down sequence control
Fault event handling
Interrupt generation on warnings
Watchdog function can be integrated in the SE
Program software control of sequencing through the SMBus
Complete voltage margining solution for 6 voltage rails
6 output voltage 8-bit DACs (0.300 V to 1.552 V) allow voltage
adjustment via dc-to-dc converter trim/feedback node
12-bit ADC for readback of all supervised voltages
Reference input (REFIN) with two input options
Driven directly from the 2.048 V (±0.25%) REFOUT pin
External reference for improved ADC performance
Powered by the highest voltage on either VPx or VH
Voltage on VPx or VH must be greater than the
undervoltage lockout (UVLO) threshold
Electronically erasable programmable read-only memory
(EEPROM)
Industry-standard, 2-wire bus interface (SMBus)
PDOx pins guaranteed low with VH and VPx = 1.2 V
Available in a 40-lead, 6 mm × 6 mm LFCSP package
FUNCTIONAL BLOCK DIAGRAM
REFOUT REFGND
REFIN CDA
CCL SDA SCL A1 A0
VX1
VX2
VX3
VX4
VX5
VP1
VP2
VP3
VP4
VH
AGND
VREF
ADM1260
INTERCHIP
BUS
12-BIT
SAR ADC
CLOSED-LOOP
MARGINING SYSTEM
DUAL-
FUNCTION
INPUTS
(LOGIC INPUTS
OR
SFDs)
SEQUENCING
ENGINE
PROGRAMMABLE
RESET
GENERATORS
(SFDs)
VOUT VOUT VOUT VOUT VOUT VOUT
DAC DAC DAC DAC DAC DAC
SMBus
INTERFACE
EEPROM
FAULT
RECORDING
CONFIGURABLE
OUTPUT
DRIVERS
(HV CAPABLE OF
DRIVING GATES
OF N-FET)
CONFIGURABLE
OUTPUT
DRIVERS
(LV CAPABLE
OF DRIVING
LOGIC SIGNALS)
VDD
ARBITRATOR
PDO1
PDO2
PDO3
PDO4
PDO5
PDO6
PDO7
PDO8
PDO9
PDO10
PDOGND
VDDCAP
DAC1 DAC2 DAC3 DAC4 DAC5 DAC6
Figure 1.
VCCP GND
APPLICATIONS
Central office systems
Servers/routers
Multivoltage system line cards
Digital signal processor (DSP)/field programmable gate
array (FPGA) supply sequencing
In-circuit testing of margined supplies
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com


ADM1260 데이터시트, 핀배열, 회로
ADM1260
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1 
Functional Block Diagram .............................................................. 1 
Applications....................................................................................... 1 
Revision History ............................................................................... 3 
General Description ......................................................................... 4 
Detailed Functional Block Diagram .............................................. 4 
Specifications..................................................................................... 5 
Absolute Maximum Ratings............................................................ 9 
Thermal Resistance ...................................................................... 9 
ESD Caution.................................................................................. 9 
Pin Configuration and Function Descriptions........................... 10 
Typical Performance Characteristics ........................................... 11 
Test Circuits..................................................................................... 14 
Powering the ADM1260 ................................................................ 15 
Slew Rate Considerations .......................................................... 15 
Inputs................................................................................................ 16 
Supply Supervision..................................................................... 16 
Programming the Supply Fault Detectors............................... 16 
Input Comparator Hysteresis.................................................... 16 
Input Glitch Filtering ................................................................. 17 
Supply Supervision with the VXx Inputs ................................ 17 
VXx Pins as Digital Inputs ........................................................ 18 
Outputs ............................................................................................ 19 
Supply Sequencing Through Configurable Output Drivers...... 19 
Default Output Configuration.................................................. 19 
Sequencing Engine ......................................................................... 20 
Overview...................................................................................... 20 
Warnings...................................................................................... 20 
SMBus Jump (Unconditional Jump)........................................ 20 
Interchip Bus ............................................................................... 21 
SE Application Example ............................................................ 21 
Fault and Status Reporting ........................................................ 23 
Nonvolatile Black Box Fault Recording................................... 24 
Black Box Writes with No External Supply............................. 24 
Voltage Readback............................................................................ 25 
Supply Supervision with the ADC ........................................... 25 
Supply Margining ........................................................................... 26 
Overview...................................................................................... 26 
Open-Loop Supply Margining ................................................. 26 
Closed-Loop Supply Margining ............................................... 26 
Writing to the DACs .................................................................. 27 
Choosing the Size of the Attenuation Resistor....................... 27 
DAC Limiting and Other Safety Features ............................... 27 
Applications Information .............................................................. 28 
Multiple Devices Linked by ICB and Power Island
Management ............................................................................... 28 
Communicating with the ADM1260 ........................................... 30 
Configuration Download at Power-Up................................... 30 
Updating the Configuration ..................................................... 30 
Updating the Sequencing Engine............................................. 31 
Internal Registers........................................................................ 31 
EEPROM ..................................................................................... 31 
Serial Bus Interface..................................................................... 31 
SMBus Protocols for RAM and EEPROM.............................. 33 
Write Operations ........................................................................ 34 
Read Operations......................................................................... 35 
Interchip Bus ................................................................................... 37 
Overview ..................................................................................... 37 
Message Formats ........................................................................ 37 
ICB Addressing and Event ........................................................ 37 
ICB Fault Handling .................................................................... 38 
ICB Pull-Up Resistor ................................................................. 38 
Configuration Registers................................................................. 39 
Updating the Memory, Enabling Block Erasure, and
Downloading EEPROM ............................................................ 39 
Inputs ........................................................................................... 40 
Outputs ........................................................................................ 48 
Sequencing Engine..................................................................... 54 
Configuring Sequence Engine States to Write into the Black
Box EEPROM ............................................................................. 58 
ADC ............................................................................................. 60 
DACs ............................................................................................ 63 
Warnings, Faults, and Status ..................................................... 66 
Black Box Status Registers and Fault Records ........................ 67 
Use of the REVID Register........................................................ 69 
Interchip Bus Configuration..................................................... 69 
Register Map Quick Reference ..................................................... 70 
Outline Dimensions ....................................................................... 71 
Ordering Guide .......................................................................... 71 
Rev. 0 | Page 2 of 71




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