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AD9154 반도체 회로 부품 판매점

Digital-to-Analog Converter



Analog Devices 로고
Analog Devices
AD9154 데이터시트, 핀배열, 회로
Data Sheet
Quad, 16-Bit, 2.4 GSPS, TxDAC+®
Digital-to-Analog Converter
AD9154
FEATURES
Supports input data rates up to 1 GSPS
Proprietary, low spurious and distortion design
Single carrier LTE 20 MHz bandwidth (BW), ACLR = 77 dBc at
180 MHz IF
Six carrier GSM IMD = 78 dBc, 600 kHz carrier spacing at
180 MHz IF
SFDR = 72 dBc at 180 MHz IF, −6 dBFS single tone
Flexible 8-lane JESD204B interface
Multiple chip synchronization
Fixed latency
Data generator latency compensation
Input signal power detection
High performance, low noise phase-locked loop (PLL) clock
multiplier
Digital inverse sinc filter
Digital quadrature modulation using a numerically
controlled oscillator (NCO)
Nyquist band selection—mix mode
Selectable 1×, 2×, 4×, and 8× interpolation filters
Low power: 2.11 W at 1.6 GSPS, full operating conditions
88-lead, exposed pad LFCSP
APPLICATIONS
Wireless communications
Multicarrier LTE and GSM base stations
Wideband repeaters
Software defined radios
Wideband communications
Point to point microwave radio
Transmit diversity, multiple input/multiple output (MIMO)
Instrumentation
Automated test equipment
GENERAL DESCRIPTION
The AD9154 is a quad, 16-bit, high dynamic range digital-to-
analog converter (DAC) that provides a maximum sample rate
of 2.4 GSPS, permitting multicarrier generation up to the Nyquist
frequency in baseband mode. The AD9154 includes features
optimized for direct conversion transmit applications, including
complex digital modulation, input signal power detection, and
gain, phase, and offset compensation. The DAC outputs are
optimized to interface seamlessly with the ADRF6720-27 radio
frequency quadrature modulator (AQM) from Analog Devices,
Inc. In mix mode, the AD9154 DAC can reconstruct carriers in
the second and third Nyquist zones. A serial port interface (SPI)
provides the programming/readback of internal parameters.
The full-scale output current can be programmed over a range
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
FUNCTIONAL BLOCK DIAGRAM
QUAD MOD
ADRF6720-27
DAC
RF
OUTPUT
0°/90° PHASE
SHIFTER
LPF
DAC
JESD204B
SYNCOUTx±
SYSREF
LO_IN
MOD_SPI
QUAD MOD
ADRF6720-27
QUAD DAC
DAC
RF
OUTPUT 1
0°/90° PHASE
SHIFTER
LPF
LO_IN
DAC
AD9154
MOD_SPI
DAC DAC
CLOCK SPI
Figure 1.
JESD204B
SYNCOUTx±
of 4 mA to 20 mA. The AD9154 is available in two different
88-lead LFCSP packages.
PRODUCT HIGHLIGHTS
1. Ultrawide signal bandwidth enables emerging wideband
and multiband wireless applications.
2. Advanced low spurious and distortion design techniques
provide high quality synthesis of wideband signals from
baseband to high intermediate frequencies.
3. JESD204B Subclass 1 support simplifies multichip
synchronization.
4. Small package size with a 12 mm × 12 mm footprint.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com


AD9154 데이터시트, 핀배열, 회로
AD9154
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 3
Detailed Functional Block Diagram .............................................. 4
Specifications..................................................................................... 5
DC Specifications ......................................................................... 5
Digital Specifications ................................................................... 6
Maximum DAC Update Rate Speed Specifications by Supply.... 7
JESD204B Serial Interface Speed Specifications ...................... 7
SYSREF to DAC Clock Timing Specifications ......................... 8
Digital Input Data Timing Specifications ................................. 8
Latency Variation Specifications ................................................ 9
JESD204B Interface Electrical Specifications ........................... 9
AC Specifications........................................................................ 10
Absolute Maximum Ratings.......................................................... 11
Thermal Resistance .................................................................... 11
ESD Caution................................................................................ 11
Pin Configuration and Function Descriptions........................... 12
Typical Performance Characteristics ........................................... 14
Terminology .................................................................................... 20
Theory of Operation ...................................................................... 21
Serial Port Operation ..................................................................... 22
Link Latency Setup..................................................................... 30
Crossbar Setup............................................................................ 32
JESD204B Serial Data Interface.................................................... 33
JESD204B Overview .................................................................. 33
Physical Layer ............................................................................. 34
Data Link Layer .......................................................................... 37
Transport Layer .......................................................................... 45
JESD204B Test Modes ............................................................... 58
JESD204B Error Monitoring..................................................... 59
Digital Datapath ............................................................................. 62
Dual Paging................................................................................. 62
Data Format ................................................................................ 62
Interpolation Modes .................................................................. 62
Digital Modulation..................................................................... 63
Inverse Sinc ................................................................................. 64
Digital Gain, Phase Adjust, DC Offset, and Group Delay.... 64
I to Q Swap .................................................................................. 65
NCO Alignment ......................................................................... 65
Downstream Protection ............................................................ 66
Datapath PRBS ........................................................................... 68
DC Test Mode............................................................................. 69
Interrupt Request Operation ........................................................ 70
Interrupt Service Routine.......................................................... 70
DAC Input Clock Configurations ................................................ 72
Driving the CLK± Inputs .......................................................... 72
Data Format ................................................................................ 22
Serial Port Pin Descriptions...................................................... 22
Serial Port Options ..................................................................... 22
Chip Information............................................................................ 24
Device Setup Guide ........................................................................ 25
Step 1: Start Up the DAC........................................................... 25
Step 2: Digital Datapath............................................................. 26
Step 3: Transport Layer.............................................................. 26
Step 4: Physical Layer................................................................. 27
Step 5: Data Link Layer.............................................................. 28
Step 6: Error Monitoring ........................................................... 28
DAC PLL Setup............................................................................ 28
Interpolation ............................................................................... 29
JESD204B Setup.......................................................................... 29
Equalization Mode Setup .......................................................... 30
DAC PLL Fixed Register Writes............................................... 72
Condition Specific Register Writes.......................................... 72
Starting the PLL.......................................................................... 73
Analog Outputs............................................................................... 75
Transmit DAC Operation.......................................................... 75
Normal and Mix Modes of Operation..................................... 76
Temperature Sensor ....................................................................... 77
Example Start-Up Sequence.......................................................... 78
Step 1: Start Up the DAC........................................................... 78
Step 2: Digital Datapath............................................................. 78
Step 3: Transport Layer.............................................................. 79
Step 4: Physical Layer................................................................. 79
Step 5: Data Link Layer.............................................................. 80
Step 6: Error Monitoring ........................................................... 80
Board Level Hardware Considerations........................................ 81
Rev. B | Page 2 of 124




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