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PDF AD9102 Data sheet ( Hoja de datos )
| Número de pieza | AD9102 | |
| Descripción | Digital to Analog Converter and Waveform Generator | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
Low Power, 14-Bit, 180 MSPS, Digital-to-Analog
Converter and Waveform Generator
AD9102
FEATURES
On-chip 4096 × 14-bit pattern memory
On-chip DDS
Power dissipation @ 3.3 V, 4 mA output
96.54 mW @ 180 MSPS
Sleep mode: <5 mW @ 3.3 V
Supply voltage: 1.8 V to 3.3 V
SFDR to Nyquist
87 dBc @ 10 MHz output
Phase noise @ 1 kHz offset, 180 MSPS, 8 mA: −150 dBc/Hz
Differential current outputs: 8 mA max @ 3.3 V
Small footprint, 32-lead, 5 mm × 5 mm LFCSP with 3.6 mm ×
3.6 mm exposed paddle, and Pb-free package
APPLICATIONS
Medical instrumentation
Portable instrumentation
Signal generators, arbitrary waveform generators
Automotive radar
GENERAL DESCRIPTION
The AD9102 TxDAC® and waveform generator is a high perfor-
mance digital-to-analog converter (DAC) integrating on-chip
pattern memory for complex waveform generation with a direct
digital synthesizer (DDS).
The DDS is a 14-bit output, up to 180 MSPS master clock sine
wave generator with a 24-bit tuning word, allowing 10.8 Hz/LSB
frequency resolution.
SRAM data can include directly generated stored waveforms,
amplitude modulation patterns applied to DDS outputs, or DDS
frequency tuning words.
An internal pattern control state machine lets the user program
the pattern period for the DAC as well the start delay within the
pattern period for the signal output on the DAC .
A SPI interface is used to configure the digital waveform
generator and load patterns into the SRAM.
A gain adjustment factor and an offset adjustment are applied to
the digital signal on their way into the DAC.
The AD9102 offers exceptional ac and dc performance and
supports DAC sampling rates of up to 180 MSPS.
The flexible power supply operating range of 1.8 V to 3.3 V and
low power dissipation of the AD9102 make it well suited for
portable and low power applications.
PRODUCT HIGHLIGHTS
1. High Integration.
On-chip DDS and 4096 × 14 pattern memory.
2. Low Power.
Power-down mode provides for low power idle periods.
FUNCTIONAL BLOCK DIAGRAM
TRIGGER
AD9102
START ADDR
START DELAY
STOP ADDR
DAC
TIMERS + STATE MACHINE
ADDRESS
SPI
INTERFACE
10kΩ
1V
BAND
GAP
GAIN OFFSET
IREF
100µA
SRAM
1.8V
LDOs
PHASE
TUNING WORD
DAC CLOCK
DDS
DDS
1.8V
LDO
CLOCK
DIST
RSET1
16kΩ
DAC
AGND
IOUTP
IOUTN
AVDD1
AVDD2
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2013 Analog Devices, Inc. All rights reserved.
1 page  
AD9102
Data Sheet
DC SPECIFICATIONS (1.8 V)
TMIN to TMAX; AVDD = 1.8 V; DVDD = DLDO1 = DLDO2 = 1.8 V; CLKVDD = CLDO = 1.8 V; IOUTFS = 4 mA; maximum sample rate, unless
otherwise noted.
Table 2.
Parameter
RESOLUTION
ACCURACY @ 1.8 V
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
DAC OUTPUTS
Offset Error
Gain Error Internal Reference—No Automatic IOUTFS Calibration
Full-Scale Output Current
VCC = 1.8 V
Output Resistance
Output Compliance Voltage
DAC TEMPERATURE DRIFT
Gain
Reference Voltage
REFERENCE OUTPUT
Internal Reference Voltage with AVDD = 1.8 V
Output Resistance
REFERENCE INPUT
Voltage Compliance
Input Resistance External Reference Mode
Min Typ Max Unit
14 Bits
±1.5 LSB
±1.4 LSB
±0.00025
% of FSR
−1.0 +1.0 % of FSR
2 4 4 mA
200 MΩ
−0.5 +1.0 V
±228
±131
ppm/°C
ppm/°C
0.8 1.0 1.2 V
10 kΩ
0.1
1
1.25 V
MΩ
DIGITAL TIMING SPECIFICATIONS (3.3 V)
TMIN to TMAX; AVDD = 3.3 V; DVDD = 3.3 V, CLKVDD = 3.3 V, internal CLDO, DLDO1, and DLDO2; IOUTFS = 8 mA; maximum sample rate,
unless otherwise noted.
Table 3.
Parameter
DAC CLOCK INPUT (CLKIN)
Maximum Clock Rate
SERIAL PERIPHERAL INTERFACE
Maximum Clock Rate (SCLK)
Minimum Pulse Width High
Minimum Pulse Width Low
Setup Time SDIO to SCLK
Hold Time SDIO to SCLK
Output Data Valid SCLK to SDO/SDI2/DOUT or SDIO
Setup Time CS to SCLK
Min Typ Max Unit
180 MSPS
80
6.25
6.25
4.0
5.0
6.2
4.0
MHz
ns
ns
ns
ns
ns
ns
Rev. 0 | Page 4 of 36
5 Page 
AD9102
Pin No.
29
30
31
32
Mnemonic
AVDD1
NC
NC
TRIGGER
EPAD
Data Sheet
Description
1.8 V to 3.3 V Power Supply Input for DAC.
Not Connected. Do not connect to this pin.
Not Connected. Do not connect to this pin.
Pattern Trigger Input.
Exposed Pad. It is recommended that the exposed pad be thermally connected to a copper ground plane for
enhanced electrical and thermal performance.
Rev. 0 | Page 10 of 36
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9102.PDF ] | |
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