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Intersil Corporation |
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3A Digital-DC Synchronous Step-Down DC/DC
Converter
ZL2103
The ZL2103 is an innovative power conversion and
management IC that combines an integrated synchronous
step-down DC/DC converter with key power management
functions in a small package, resulting in a flexible and
integrated solution.
The ZL2103 can provide an output voltage from 0.54V to 5.5V
(with margin) from an input voltage between 4.5V and 14V.
Internal low rDS(ON) synchronous power MOSFETs enable the
ZL2103 to deliver continuous loads up to 3A with high
efficiency. An internal Schottky bootstrap diode reduces
discrete component count. The ZL2103 also supports phase
spreading to reduce system input capacitance.
Power management features such as digital soft-start delay
and ramp, sequencing, tracking, and margining can be
configured by simple pin-strapping or through an on-chip serial
port. The ZL2103 uses the PMBus™ protocol for
communication with a host controller and the Digital-DC bus
for interoperability between other Zilker Labs devices.
Features
• Integrated MOSFET switches
• 3A continuous output current
• ±1% output voltage accuracy
• Snapshot™ parametric capture
• I2C/SMBus interface, PMBus compatible
• Internal non-volatile memory (NVM)
Applications*(see page 27)
• Telecom, Networking, Storage equipment
• Test and Measurement equipment
• Industrial control equipment
• 5V and 12V distributed power systems
Related Literature
• See AN2010 “Thermal and Layout Guidelines for Digital-
DC™ Products”
• See AN2033 “Zilker Labs PMBus Command Set-DDC
Products PMBus Command Set”
• See AN2035 “Compensation Using CompZL™”
100
VOUT = 3.3V
90
80
70
60
50
VIN = 12V
fSW = 200kHz
L = 6µH
40
0.0 0.5 1.0 1.5 2.0
IOUT (A)
FIGURE 1. ZL2103 EFFICIENCY
2.5
3.0
May 3, 2011
FN6966.5
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
Datasheet pdf - http://www.DataSheet4U.net/
www.DataSheet.co.kr
ZL2103
Typical Application Circuit
The following application circuit represents a typical
implementation of the ZL2103. For PMBus operation, it is
recommended to tie the enable pin (EN) to SGND.
DDC Bus†
ENABLE
C25
10µF
CRA
4.7µF
F.B.‡
CR
4.7µF
CDD
2.2µF
VIN
12V
CIN
100µF
PGOOD
I2C/
SMBus††
1 PG
2 DGND
3 SYNC
4 VSET
5 SA
6 SCL
7 SDA
8 SALRT
9 FC
ZL2103
VDDP 27
BST 26
SW 25
SW 24
SW 23
SW 22
SW 21
SW 20
PGND 19
CB
47nF
LOUT
2.2µH
COUT
150µF
VOUT
3.3V
Notes:
‡ Ferrite bead is optional for input noise suppression.
† The DDC bus pull-up resistance will vary based on the capacitive loading of the bus, including the number of devices
connected. The 10 k♦Ω default value, assuming a maximum of 100 pF per device, provides the necessary 1 µs pull-up rise
time. Please refer to the Digital-DC Bus section for more details.
†† The I2C/SMBus pull-up resistance will vary based on the capacitive loading of the bus, including the number of devices
connected. Please refer to the I2C/SMBus specifications for more details.
FIGURE 2. 12V TO 3.3V/3A APPLICATION CIRCUIT (5ms SS DELAY, 5ms SS RAMP)
Block Diagram
VIN
EN
PG
MGN
VSET
CFG
SS
VTRK
DDC
SA
2.5V
LDO
5V
LDO
7V
LDO
Power
Mgmt
PWM
Control
&
Drivers
DDC Bus
SMBus
NVM
BST
SW
VSEN
VOUT
FIGURE 3. BLOCK DIAGRAM
2
FN6966.5
May 3, 2011
Datasheet pdf - http://www.DataSheet4U.net/
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