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PDF AD9125 Data sheet ( Hoja de datos )
| Número de pieza | AD9125 | |
| Descripción | TxDAC+ Digital-to-Analog Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Dual, 16-Bit, 1000 MSPS,www.DataSheet4U.com
TxDAC+ Digital-to-Analog Converter
AD9125
FEATURES
Flexible CMOS interface allows dual-word, word, or byte load
Single-carrier W-CDMA ACLR = 80 dBc at 122.88 MHz IF
Analog output: adjustable 8.7 mA to 31.7 mA, RL = 25 Ω to 50 Ω
Novel 2×/4×/8× interpolator/complex modulator allows
carrier placement anywhere in the DAC bandwidth
Gain and phase adjustment for sideband suppression
Multichip synchronization interface
High performance, low noise PLL clock multiplier
Digital inverse sinc filter
Low power: 900 mW at 500 MSPS, full operating conditions
72-lead, exposed paddle LFCSP
APPLICATIONS
Wireless infrastructure
W-CDMA, CDMA2000, TD-SCDMA, WiMAX, GSM, LTE
Digital high or low IF synthesis
Transmit diversity
Wideband communications: LMDS/MMDS, point-to-point
Cable modem termination systems
GENERAL DESCRIPTION
The AD9125 is a dual, 16-bit, high dynamic range TxDAC+®
digital-to-analog converter (DAC) that provides a sample rate of
1000 MSPS, permitting a multicarrier generation up to the Nyquist
frequency. It includes features optimized for direct conversion
transmit applications, including complex digital modulation,
and gain and offset compensation. The DAC outputs are optimized
to interface seamlessly with analog quadrature modulators, such
as the ADL537x F-MOD series from Analog Devices, Inc. A 4-wire
serial port interface allows programming/readback of many inter-
nal parameters. Full-scale output current can be programmed
over a range of 8.7 mA to 31.7 mA. The AD9125 comes in a
72-lead LFCSP.
PRODUCT HIGHLIGHTS
1. Ultralow noise and intermodulation distortion (IMD)
enable high quality synthesis of wideband signals from
baseband to high intermediate frequencies.
2. A proprietary DAC output switching technique enhances
dynamic performance.
3. The current outputs are easily configured for various
single-ended or differential circuit topologies.
4. The flexible CMOS digital interface allows the standard
32-wire bus to be reduced to a 16-wire bus.
COMPLEX BASEBAND
TYPICAL SIGNAL CHAIN
COMPLEX IF
RF
DC fIF
DIGITAL
BASEBAND
PROCESSOR
2
SIN
COS
2
2/4 I DAC
2/4 Q DAC
NOTES
1. AQM = ANALOG QUADRATURE MODULATOR.
Figure 1.
LO – fIF
ANTIALIASING
FILTER
AQM PA
LO
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2010 Analog Devices, Inc. All rights reserved.
1 page  
AD9125www.DataSheet4U.com
DIGITAL SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, IOVDD = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless
otherwise noted.
Table 2.
Parameter
CMOS DATA INPUTS
Input VIN Logic High
Input VIN Logic Low
Maximum Bus Speed
SERIAL PORT OUTPUT LOGIC LEVELS
Output VOUT Logic High
Output VOUT Logic Low
SERIAL PORT INPUT LOGIC LEVELS
Input VIN Logic High
Input VIN Logic Low
DACCLK INPUT (DACCLKP, DACCLKN)
Differential Peak-to-Peak Voltage
Common-Mode Voltage
Maximum Clock Rate
REFCLK INPUT (REFCLKP, REFCLKN)
Differential Peak-to-Peak Voltage
Common-Mode Voltage
REFCLKx Frequency, PLL Mode
REFCLKx Frequency, SYNC Mode
SERIAL PERIPHERAL INTERFACE
Maximum Clock Rate (SCLK)
Minimum Pulse Width High (tPWH)
Minimum Pulse Width Low (tPWOL)
Setup Time, SDI to SCLK (tDS)
Hold Time, SDI to SCLK (tDH)
Data Valid, SDO to SCLK (tDV)
Setup Time, CS to SCLK (tDCS)
Conditions
Min Typ Max Unit
1.2 V
0.6 V
250 MHz
IOVDD = 1.8 V
IOVDD = 2.5 V
IOVDD = 3.3 V
IOVDD = 1.8 V
IOVDD = 2.5 V
IOVDD = 3.3 V
1.4 V
1.8 V
2.0 V
0.4
0.4 V
0.4 V
IOVDD = 1.8 V
IOVDD = 2.5 V
IOVDD = 3.3 V
IOVDD = 1.8 V
IOVDD = 2.5 V
IOVDD = 3.3V
1.2 V
1.6 V
2.4 V
0.6 V
0.8 V
0.8 V
Self biased input, ac couple
100
1000
500 2000 mV
1.25 V
MHz
100 500 2000 mV
1.25 V
1 GHz ≤ fVCO ≤ 2.1 GHz
15.625
600 MHz
See the Multichip Synchronization section for conditions 0
600 MHz
40 MHz
12.5 ns
12.5 ns
1.9 ns
0.2 ns
2.3 ns
1.4 ns
LATENCY AND POWER-UP TIMING SPECIFICATIONS
Table 3.
Parameter
LATENCY (DACCLK Cycles)
1× Interpolation (with or Without Modulation)
2× Interpolation (with or Without Modulation)
4× Interpolation (with or Without Modulation)
8× Interpolation (with or Without Modulation)
Inverse Sinc
Fine Modulation
Power-Up Time
Rev. 0 | Page 5 of 56
Min Typ Max
64
135
292
608
20
8
260
Unit
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
ms
5 Page 
–50
fDATA = 125MSPS
–55 fDATA = 250MSPS
–60
–65
–70
–75
–80
–85
–90
–95
0
50 100 150 200 250 300
fOUT (MHz)
Figure 10. Highest Digital Spur vs. fOUT over fDATA, 2× Interpolation,
Digital Scale = 0 dBFS, fSC = 20 mA
–50
fDATA = 125MSPS
–55 fDATA = 250MSPS
–60
–65
–70
–75
–80
–85
–90
0
100 200 300 400 500 600
fOUT (MHz)
Figure 11. Highest Digital Spur vs. fOUT over fDATA, 4× Interpolation,
Digital Scale = 0 dBFS, fSC = 20 mA
–50
fDATA = 125MSPS
–55
–60
–65
–70
–75
–80
–85
–90
–95
0
50 100 150 200 250 300 350 400
fOUT (MHz)
Figure 12. Highest Digital Spur vs. fOUT over fDATA, 8× Interpolation,
Digital Scale = 0 dBFS, fSC = 20 mA
AD9125www.DataSheet4U.com
2× INTERPOLATION,
SINGLE-TONE SPECTRUM,
fDATA = 250MSPS,
fOUT = 101MHz
START 1.0MHz
#RES BW 10kHz
VBW 10kHz
STOP 500.0MHz
SWEEP 6.017s (601 PTS)
Figure 13. 2× Interpolation, Single-Tone Spectrum
4× INTERPOLATION,
SINGLE-TONE SPECTRUM,
fDATA = 125MSPS,
fOUT = 101MHz
START 1.0MHz
#RES BW 10kHz
VBW 10kHz
STOP 500.0MHz
SWEEP 6.017s (601 PTS)
Figure 14. 4× Interpolation, Single-Tone Spectrum
8× INTERPOLATION,
SINGLE-TONE SPECTRUM,
fDATA = 125MSPS,
fOUT = 131MHz
START 1.0MHz
#RES BW 10kHz
VBW 10kHz
STOP 1.0GHz
SWEEP 12.05s (601 PTS)
Figure 15. 8× Interpolation, Single-Tone Spectrum
Rev. 0 | Page 11 of 56
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9125.PDF ] | |
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