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PDF IP113ALF Data sheet ( Hoja de datos )
| Número de pieza | IP113ALF | |
| Descripción | 10 /100Base-Tx/Fx Media Converter | |
| Fabricantes | ICp | |
| Logotipo |  |
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IP113A LF
Preliminary Data Sheet
10 /100Base-Tx/Fx Media Converter
Features
A 10/100BASE-TX/ 100BASE-FX converter
Built in a 10/100BASE-TX transceiver
Built in a PHY for 100BASE-FX
Built in a 2-port switch
– Pass all packets without address and
CRC check (optional)
– Supports modified cut-through frame
forwarding for low latency
– Supports pure converter mode data
forwarding for extreme low latency
– Supports flow control for full and half
duplex operation
– Bandwidth control
– Forward 1600 bytes packet for
management
– Optional forward fragments
Built in 128Kb RAM for data buffer
Supports auto MDI-MDIX function
Supports link fault pass through function
Supports far end fault function
LED display for link/activity, full/half, 10/100
Built in a watchdog timer to monitor internal
switch error
Supports EEPROM Configuration
0.25u CMOS technology
Single 2.5V power supply
48-pin LQFP package
Support Lead Free package (Please refer to
the Order Information)
General Description
IP113A LF can be a 10/100BASE-TX to
100BASE-FX converter. It consists of a 2-port
switch controller, a fast Ethernet transceiver and a
PHY for 100BASE-FX. The transceivers in IP113A
LF are designed in DSP approach with advance
0.25-um technology; this results in high noise
immunity and robust performance.
IP113A LF not only supports store and forward
mode, it also supports modified cut through mode
and pure converter mode for low latency data
forwarding. IP113A LF can transmit packet(s) up
to 1600 bytes to meet requirement of extra long
packets.
IP113A LF supports IEEE802.3x, collision base
backpressure, and various LED functions, etc.
These functions can be configured to fit the
different requirements by feeding operation
parameters via EEPROM interface or pull
up/down resistors on specified pins.
Copyright © 2004, IC Plus Corp.
1/22
April 9, 2007
IP113A LF-DS-R08
1 page  
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1. PIN Description
Type
I
O
IPL
IPH
Description
Input pin
Output pin
Input pin with internal pull-low resistor.
Input pin with internal pull-high resistor.
IP113A LF
Preliminary Data Sheet
Pin no.
Label
Transceiver
5, 6 RXIP, RXIM
8, 9 TXOP, TXOM
2 BGRES
18 FXSD
13, 14
FXRDP, FXRDM
16, 17
FXTDP, FXTDM
Type
Description
I TP receive
O TP transmit
O Band gap resistor
It is connected to GND through a 6.19k (1%) resistor in
application circuit.
I 100Base-FX signal detect
Fiber signal detect. It is an input signal from fiber MAU.
Fiber signal detect is active if the voltage on FXSD is higher
than the threshold voltage, which is 1.35v ±5% when VCC
is equal to 2.5v.
I Fiber receiver data pair
Common-mode voltage of FXRDP and FXRDM are
suggested to near 0.5x AVCC.
When voltage peak-to-peak>0.1V,FXRX could be
workable.
O Fiber transmitter data pair
FXTX with the external 100Ω resistor.
Common-mode voltage of FXTDP and FXTDM are
suggested to near 0.5x AVCC.
Swing of Voltage ≧ 0.8V.
Copyright © 2004, IC Plus Corp.
5/22
April 9, 2007
IP113A LF-DS-R08
5 Page 
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IP113A LF
Preliminary Data Sheet
2. Functional Description
Data forwarding
IP113A LF supports three types of data forwarding mode, store & forward mode, modified cut-through
mode and pure converter mode. It can forward a frame despite of its address and CRC error. IP113A LF
begins to forward the received data only after it receives the frame completely. The latency depends on
the packet length.
Modified cut-through mode
IP113A LF begins to forward the received data when it receives the first 64 bytes of the frame. The
latency is about 512 bits time width. The maximum packet length can be up to1600 bytes in this mode.
Please refer to the pin description of FAST_FWD for configuration information.
Pure converter mode
IP113A LF operates with the minimum latency in this mode. The transmission flow does not wait until
entire frame is ready, but instead it forwards the received data immediately after the data being received.
Both transceivers are interconnected via internal MII signals, therefore the internal switch engine and
data buffer are not used. Both TP port and fiber port of IP113A LF should work at 100M full duplex in this
mode. If TP port is linked at half duplex, the total length of UTP cable and fiber should be less than 60
meters to meet the requirement of CSMACD in IEEE802.3.The packet length is not limited at this mode.
Please see pin description of DIRECT_WIRE for configuration information.
Fragment forwarding
IP113A LF forwards CRC error packets but it will filter fragments when it works in modified cut-through
mode. IP113A LF forwards fragments if user turns on bit 3 of EEPROM register 2.
Copyright © 2004, IC Plus Corp.
11/22
April 9, 2007
IP113A LF-DS-R08
11 Page | ||
| Páginas | Total 22 Páginas | |
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