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PDF ZR36016 Data sheet ( Hoja de datos )
| Número de pieza | ZR36016 | |
| Descripción | INTEGRATED COLOR SPACE / RASTER-TO-BLOCK CONVERTER | |
| Fabricantes | Zoran | |
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ZR36016
PwRwEw.LDMatIaNSAheReYt4U.comINTEGRATED COLOR SPACE / RASTER-TO-BLOCK CONVERTER
FEATURES
s Raster-to-block and block-to-raster conversions with strip
buffer of external SRAMs.
s Color space conversions of RGB to/from YCbCr or YeMaCy.
s Supports Fast Preview expansion and Lossless Compres-
sion/Expansion modes of the ZR36050.
s Exclusive dual pixel buses. Separate format and color space
conversions on the ZR36050 data and output data during
compression and expansion.
s Supports 4:4:4, 4:4:4:4, 4:2:2, 4:1:1 and 1:0:0 I/O formats.
s Supports many format conversions between pixel input bus
and pixel output bus, pixel input bus and ZR36050, and
ZR36050 and pixel output bus.
s Supports filtering for image format conversions.
s Horizontal decimation/interpolation with optional filtering and
vertical decimation/interpolation by line dropping or
replication.
s Enable function of pixel I/O buses for asynchronous
applications.
s Sequential processing mode simplifies motion JPEG
implementation.
s Provides windowing function to select processing area.
s TTL levels for Input/Output.
s 160 pin PQFP.
DESCRIPTION
The ZR36016 is a pre- and post-processor for use with a
ZR36050 JPEG Image Codec, performing raster-to-block reor-
dering and color space conversion.
The ZR36016 accepts input pixels in a variety of common color
spaces. The pixel data can undergo format and color space con-
version, with converted data available on the pixel output bus
(Figure 1). When compressing, the data fed to the ZR36050 can
be cropped within a selected window area, and its format can be
different from that of the pixel output bus. For instance, it is
possible to output an RGB(4:4:4) input onto the pixel output bus
and to feed the ZR36050 with a YbCr(4:2:2) format. It is also
possible to output a YCbCr(4:2:2) format input as RGB(4:4:4)
and to feed the ZR36050 with a YCbCr(4:1:1) format. During
expansion, for instance, the ZR36016 can output an RGB(4:4:4)
input directly onto the output pixel bus, and after converting YCb-
Cr(4:2:2) format coming from the ZR36050 into RGB(4:4:4), it
overlays it in a window on the pixel input data.
The ZR36016 uses an external SRAM double-strip buffer for
raster-block conversions and block interleaving. The Fast
Preview and Lossless modes of operation of the ZR36050 are
also supported, in which case the SRAM is used only for raster-
to-raster buffering and pixel interleaving. Depending on the
SRAM size and the mode of operation, the maximum line length
can be up to 64K pixels. The number of lines per image can be
up to 64K.
Processing of data on the pixel buses can be continuous as
required for live frame capture or Motion JPEG, or it can be dis-
continuous, with pixels transferred only when enabled by an
enable signal.
The data transfer rate with the ZR36050 is at a maximum of
30 MHz, the system clock rate. The pixel buses transfer at a
maximum of 30 MHz for 4:0:0, or at a frequency ratio of 1, 1/2 or
1/4 of the system clock for the other formats, depending on the
format conversions that are selected.
As shown in Figure 2, the input pixel data pass through a multi-
plexer, to the color space convertor. In compression, this
multiplexer always passes the pixel data (the top input). The
output of the color space convertor takes two paths in compres-
sion, one to the pixel output bus and the other to the raster to
block convertor. The data on each path can independently
undergo format conversion, which in this context means a reso-
lution transformation by decimation or interpolation, of the
chrominance components; for example, decimation from
PXIN
Color Space Conversion
Format Conversion
Window Management
Raster-to-Block
ZR36050
Compression
PXOUT
PXIN
Color Space Conversion
Format Conversion
Window Management
Block-to-Raster
ZR36050
Expansion
Figure 1. ZR36016 Operations with a ZR36050
PXOUT
ZORAN Corporation s 1705 Wyatt Drive s Santa Clara, CA 95054 s (408) 986-1314 s FAX (408) 986-1240
This document was created with FrameMaker 4.0.4
July 1995
1 page  
Integrated Color Space / Raster-To-Block Converter
Mode Register
wwRwe.Dada/tWaSrihteeet4UD.icreocmt address: 0x01
Initial Value 0x91
Function
Determines the basic operating modes and formats
of the ZR36016.
76543210
CMPR
DSPY
MODE
Bit 0-4 MODE: Determines the PXIN input and ZR36050
image formats and color spaces. Initial Value =
0x11.
PXBIN Bus
ZR36050 Image Format
Input (Compression)
Output (Expansion)
MODE
(HEX)
Image
Format
Color
Space
Image
Format
Color Space
00 4:4:4
RGB
4:4:4
YCbCr
01
4:2:2
YCbCr
02
03 [1]
4:1:1 (H2V2)
4:0:0
YCbCr
Y Only
04
4:4:4
RGB
05~07
Reserved
08
4:4:4
YCbCr
4:4:4
YCbCr
09
4:2:2
YCbCr
0A
0B [1]
4:1:1 (H2V2)
4:0:0
YCbCr
Y Only
0C
4:4:4
RGB
0D~10
Reserved
11
4:2:2
YCbCr
4:2:2
YCbCr
12
13 [1]
4:1:1 (H2V2)
4:0:0
YCbCr
Y Only
14, 15
Reserved
16
17 [1]
4:1:1
(PHILIPS)
YCbCr
4:1:1 (H4V1)
4:0:0
YCbCr
Y Only
18 Reserved
19 4:4:4:4
–
4:4:4:4
–
1A Reserved
1B 1:0:0
–
1:0:0
–
1C~1F
Reserved
1. For Compression Only. If programmed for expansion,
then MODE = 0x16 is assumed.
2. RGB becomes YeMaCy when selected by the YMCS
bit in Setup Register 2.
3. MODE = 0x16 and 0x17 are the Philips 4:1:1 format.
Input and output pixel data use the upper 12 bits of
PXIN and PXOUT buses.
4. 4:1:1(H4V1) refers to a format in which the Cb and Cr
are decimated by 4 horizontally. 4:1:1(H2V2) refers to
a format in which the Cb and Cr are decimated by 2
horizontally and 2 vertically (sometimes known as
4:2:0 format).
5. The image format conversions implied by this table
are performed by Format Converter #1 in the block
diagram.
Mode Register (Continued)
Bits 5-6 DSPY: Determines the PXOUT bus output formats.
Initial Value = 0x00.
Setting this field of the Mode register selects the
output data format of the PXOUT bus, for each
format of the PXIN bus as selected by the MODE
field of the register, as shown in the table below.
DSPY
PXIN Bus Image Format [1]
Bit Bit 4:4:4
4:4:4
4:2:2
4:1:1
6 5 (RGB) (YCbCr) (YCbCr) (Philips)
1:0:0
4:4:4:4
0 0 PXOUT is 4:4:4 (RGB) PXOUT PXOUT PXOUT
is 4:1:1 is 1:0:0 is 4:4:4
0 1 PXOUT is 4:4:4 (YCbCr) (Philips)
1 0 PXOUT is 4:2:2 (YCbCr)
11
Reserved
1. The image format conversions implied by this table
are performed by Format Converter #2 in the block
diagram.
Bit 7 CMPR: Selects compression or expansion
Initial Value = 1
0 = Expansion Mode.
1 = Compression Mode.
Setup Register 1
Read/Write Indirect address: 0x00
Initial Value 0x01
76543210
CKRT VERT HORZ HRFL DSFL SBFL RSTR CNTI
Bit 0 CNTI: Single-Frame/Sequential processing
selection.
Initial value = 1.
0= Single Frame Mode. Processes the image enabled
by VIN and then enters an idle state. For process-
ing still images.
1= Sequential Mode. Processes sequential images in-
definitely, each VIN. For Motion JPEG.
Bit 1 RSTR: Transparent mode selection, for raster/
raster conversion.
Initial Value = 0.
0= Selects the raster-to-block or block-to-raster con-
version mode.
1= Selects the transparent raster-to-raster mode.
For the Fast Preview lossless compression/expan-
sion functions of the ZR36050. The image formats
supported, as set by the MODE field, are 4:4:4:4,
4:4:4, 4:2:2, or 4:1:1 (H4V1) (with pixel interleave).
As the ZR36050 performs 1-D lossless only, the
setting of RSTR = 1 in 4:1:1(H2V2) format is not
permitted.
Note: The strip buffer processing delay is the same
for both modes.
5
5 Page 
Integrated Color Space / Raster-To-Block Converter
PXIN/PXOUT Bus Data Arrangement
TwhwewP.DXaItaNS/hPeXeOt4UU.Tcobmuses are 24 bits each. The 24 bits are
divided into 8-bit bytes, as follows.
MSB
LSB MSB
LSB MSB
LSB
PXIN/OUT[23:0]
23:16
15:8
7:0
The I/O arrangement is determined by the MODE and DSPY
fields, as shown below in Table 9. In this table, the 3 compo-
nents of (4:4:4), (4:2:2), (4:1:1), (1:0:0) formats are designated
(A:B:C), components of (4:4:4:4) format are designated
(A:B:C:D), and (A:B:C) corresponds with (R:G:B), (Y:Cb:Cr) or
(Cy:Ma:Ye). 1st, 2nd, etc., refer to the PXCLK time slots.
Table 9: I/O Bus Arrangements
PXINOUT
Bus
23-16
15-8
7-0
4:4:4
1st 2nd
AA
BB
CC
4:2:2
1st 2nd
AA
BC
––
1st
A
B[7:6]
/C[7:6]
–
I/O Format
4:1:1
2nd 3rd
AA
B[5:4]
/C[5:6]
B[3:2]
/C[3:2]
––
4th
A
B[1:0]
/C[1:0]
–
1:0:0
1st 2nd
AA
––
––
4:4:4:4
1st 2nd
AC
BD
––
4:1:1 in Table 9 is the Philips H4V1 format. As shown in
Table 10, it uses only the upper 12-bits on the PXIN/PXOUT
buses.
Table 10: Philips 4:1:1 Format
PXIN/OUT
PXIN/OUT[23:16]
PXIN/OUT[15]
PXIN/OUT[14]
PXIN/OUT[13]
PXIN/OUT[12]
PXIN/OUT[11:0]
1st
A[7:0]
B[7]
B[6]
C[7]
C[6]
–
2nd
A[7:0]
B[5]
B[4]
C[5]
C[4]
–
3rd
A[7:0]
B[3]
B[2]
C[3]
C[2]
–
4th
A[7:0]
B[1]
B[0]
C[1]
C[0]
–
PXIN/PXOUT Delay
The image data which is input on the PXIN bus is output on the
PXOUT bus after an internal delay which depends on the MODE
field and HORZ bit of the registers. The delays of VIN to VOUT
and HIN to HOUT are the same as these. See Table 11 and
Figure 5.
Table 11: PXIN to PXOUT Delay
Configuration
MD [1]
HORZ
Delay in PXCLK Clock
Cycles (d)
00
20
01
24
10
17
11
20
1. Where MD = 1 when MODE = 0x0, 0x4, 0x8 or 0xC and = 0 for all others.
HIN
PXIN n-3
n-2 n-1
n
0
1
d-3 d-2 d-1 d d+1 d+2 d+3
HOUT
PIXOUT n-3-d n-2-d n-1-d
n-d
-d
1-d
n = number of PXCLKs in one full line (HSYNC to HSYNC)
n-2 n-1
n
0
1
2
3
Figure 5. PXIN/PXOUT Delay Timing
11
11 Page | ||
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| PDF Descargar | [ Datasheet ZR36016.PDF ] | |
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