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Micro Linear Corporation |
May 1997
ML2258*
µP Compatible 8-Bit A/D Converter
with 8-Channel Multiplexer
GENERAL DESCRIPTION
The ML2258 combines an 8-bit A/D converter, 8-channel
analog multiplexer, and a microprocessor compatible 8-
bit parallel interface and control logic in a single
monolithic device.
Easy interface to microprocessors is provided by the
latched and decoded multiplexer address inputs and
latched three-state outputs.
The device is suitable for a wide range of applications
from process and machine control to consumer,
automotive, and telecommunication applications.
The ML2258 is an enhanced, pin-compatible, second
source for the industry standard ADC0808/ADC0809. The
ML2258 enhancements are faster conversion time, true
sample and hold function, superior power supply
rejection, wider reference range, and a double buffered
data bus as well as faster digital timing. All parameters
are guaranteed over temperature with a power supply
voltage of 5V ±10%.
BLOCK DIAGRAM
FEATURES
s Conversion time
6.6µs
s Total unadjusted error
±1/2LSB or ±1LSB
s No missing codes
s Sample and hold
390ns acquisition
s Capable of digitizing a 5V, 50kHz sine wave
s 8-input multiplexer
s 0V to 5V analog input range with single 5V
power supply
s Operates ratiometrically or with up to 5V
voltage reference
s No zero-or full-scale adjust required
s Analog input protection
25mA per input min
s Low power dissipation
3mA max
s TTL and CMOS compatible digital inputs and outputs
s Standard 28-pin DIP or surface mount PCC
s Superior pin compatible replacement for ADC0808 and
ADC0809
* Some Packages Are End Of Life As Of August 1, 2000
START CLOCK
IN0
IN1
IN2
IN3 8-CHANNEL
MULTIPLEXER
IN4
IN5
IN6
IN7
ADDR0
ADDR1
ADDR2
ADDRESS
LATCH ENABLE
ADDRESS
LATCH
AND
DECODER
A/D WITH
SAMPLE HOLD
CONTROL & TIMING
END OF CONVERSION
(INTERRUPT)
COMPARATOR
S.A.R.
SWITCH TREE
THREE
STATE
OUTPUT
LATCH
BUFFER
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
VCC GND +VREF
CAPACITOR/
RESISTOR
ARRAY
–VREF OUTPUT
ENABLE
1
ML2258
PIN CONFIGURATION
ML2258
28-Pin DIP (P28)
IN3
IN4
IN5
IN6
IN7
START
EOC
DB3
OE
CLK
VCC
+VREF
GND
DB1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
TOP VIEW
IN2
IN1
IN0
ADDR0
ADDR1
ADDR2
ALE
DB7
DB6
DB5
DB4
DB0
–VREF
DB2
ML2258
28-Pin PCC (Q28)
IN7
START
EOC
DB3
OE
CLK
VCC
4 3 2 1 28 27 26
5 25
6 24
7 23
8 22
9 21
10 20
11 19
12 13 14 15 16 17 18
ADDR0
ADDR1
ADDR2
ALE
DB7
DB6
DB5
TOP VIEW
PIN DESCRIPTION
PIN# NAME
1 IN3
2 IN4
3 IN5
4 IN6
5 IN7
6 START
7 EOC
8 DB3
9 OE
10 CLK
11 VCC
12 +VREF
FUNCTION
Analog input 3.
Analog input 4.
Analog input 5.
Analog input 6.
Analog input 7.
Start of conversion. Active high digital
input pulse initiates conversion.
End of conversion. This output goes
low after a START pulse occurs, stays
low for the entire A/D conversion, and
goes high after conversion is
completed. Data on DB0–DB7 is valid
on rising edge of EOC and stays valid
until next EOC rising edge.
Data output 3.
Output enable input. When OE = 0,
DB0–DB7 are in high impedance
state; OE = 1, DB0–DB7 are active
outputs.
Clock. Clock input provides timing for
A/D converter, S/H, and digital
interface.
Positive supply. 5V ± 10%.
Positive reference voltage.
PIN# NAME
13 GND
14 DB1
15 DB2
16 –VREF
17 DB0
18 DB4
19 DB5
20 DB6
21 DB7
22 ALE
23 ADDR0
24 ADDR1
25 ADDR2
26 IN0
27 IN1
28 IN2
FUNCTION
Ground. 0V, all analog and digital
inputs or outputs are reference to this
point.
Data output 1.
Data output 2.
Negative reference voltage.
Data output 0.
Data output 4.
Data output 5.
Data output 6.
Data output 7.
Address latch enable. Input to latch in
the digital address (ADDR2–0) on the
rising edge of the multiplexer.
Address input 0 to multiplexer. Digital
input for selecting analog input.
Address input 1 to multiplexer. Digital
input for selecting analog input.
Address input 2 to multiplexer. Digital
input for selecting analog input.
Analog input 0.
Analog input 1.
Analog input 2.
2
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