파트넘버.co.kr ADC-305-1 데이터시트 PDF


ADC-305-1 반도체 회로 부품 판매점

8-Bit/ 20MHz CMOS A/D Converters



ETC 로고
ETC
ADC-305-1 데이터시트, 핀배열, 회로
®®
ADC-305
8-Bit, 20MHz
CMOS A/D Converters
FEATURES
8-bit resolution, 20MHz min. sampling rate
±½LSB max. differential nonlinearity error
18MHz input signal bandwidth
Subranging, S&H enclosed
+5V single power, low 85mW max. dissipation
CMOS compatible logic input
3-State TTL compatible output
GENERAL DESCRIPTION
DATEL's ADC-305 is an 8-bit, 20MHz sampling, CMOS,
subranging (two-pass) A/D converter. It processes signals at
speeds comparable to a full flash converter by using a sub-
ranging conversion technique with multiple comparator blocks,
each containing a sample and hold amplifier.
The ADC-305 features CMOS low power dissipation (60mW
typical) and a wide 18MHz (–1dB) input signal bandwidth.
The ADC-305-1 is packaged in 400 mil 24-pin DIP and the
ADC-305-3 in 300 mil 24-pin SOP.
Other features are CMOS compatible input logic, 3-state TTL
compatible output logic, +5V single power operation, self bias
mode and low cost.
INPUT/OUTPUT CONNECTIONS
PIN FUNCTION
PIN FUNCTION
1 OUTPUT ENABLE (OE) 24 DGND
2 DGND
23 REF. BOTTOM (VRB)
3 BIT 8 (LSB)
22 SELF BIAS 1 (VRBS)
4 BIT 7
21 AGND
5 BIT 6
20 AGND
6 BIT 5
19 ANALOG INPUT (VIN)
7 BIT 4
18 +AVS (+5V)
8 BIT 3
17 REFERENCE TOP (VRT)
9 BIT 2
16 SELF BIAS 2 (VRTS)
10 BIT 1 (MSB)
15 +AVS (+5V)
11 +DVS (+5V)
14 +AVS (+5V)
12 CLOCK INPUT (A/D CLK) 13 +DVS (+5V)
Both the ADC-305-1 and the ADC-305-3 have the same pin assignment.
OUTPUT ENABLE 1
DGND 2
BIT 8 (LSB) 3
BIT 7 4
BIT 6 5
BIT 5 6
BIT 4 7
BIT 3 8
BIT 2 9
BIT 1 (MSB) 10
+DVS 11
A/D CLK 12
REFERENCE
VOLTAGE
LOWER
DATA
LATCHES
LOWER
ENCODER
(4 BIT)
UPPER
DATA
LATCHES
LOWER
ENCODER
(4 BIT)
UPPER
ENCODER
(4 BIT)
CLOCK
GENERATOR
B BLOCK
COMPARATORS
WITH S/H (4 BIT)
A BLOCK
COMPARATORS
WITH S/H (4 BIT)
UPPER
COMPARATORS
WITH S/H (4 BIT)
24 DGND
23 VRB
22 VRBS
21 AGND
20 AGND
19 VIN
18 +AVS
17 VRT
16 VRTS
15 +AVS
14 +AVS
13 +DVS
Figure 1. Functional Block Diagram
DATEL, Inc., Mansfield, MA 02048-1151 (USA) Tel: (508)339-3000, (800)233-2765 Fax: (508)339-6356 Email: [email protected] Internet www.datel.com


ADC-305-1 데이터시트, 핀배열, 회로
ADC-305
®®
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)
PARAMETERS
MIN MAX UNITS
Power Supply Voltage (+AVS, +DVS)
Analog Input Voltage (VIN)
Reference Input Voltage (VRT, VRB)
Digital Input Voltage (VIH, VIL)
Digital Output Voltage (VOH, VOL)
–0.5
–0.5
–0.5
–0.5
–0.5
+7
+AVS +0.5
+AVS +0.5
+DVS +0.5
+DVS +0.5
Volts
Volts
Volts
Volts
Volts
FUNCTIONAL SPECIFICATIONS
(Specification are typical at TA = +25°C, +VRT = +2.5V, VRB = +0.5V, +AVS = +DVS =
+5v, fS = 20MHz sampling unless otherwise specified.)
ANALOG INPUTS
Input Voltage Range (VIN) Œ
Input Capacitance
(VIN = 1.5Vdc+0.07VRMS)
Input Impedance
Input Signal Bandwidth
(VIN-2Vp-p, –1dB)
MIN.
TYP. MAX. UNITS
— +0.5 to +2.5 —
— 11 —
Volts
pF
— 12.5 — k
— 18 — MHz
REFERENCE INPUTS
Ref. Resitance VRT to VRB
Ref. Current
Ref. Voltage ΠVRT
VRB
Offset Voltage VRT
VRB
Self Bias I Œ VRBS
VRTS-VRBS
Self Bias II Œ ŽVRTS
230
4.5
+1.8
0
–10
0
+0.6
+1.96
+2.25
300
6.6
–35
+15
+0.64
+2.09
+2.39
450
8.7
+2.8
VRT
–60
+45
+0.68
+2.21
+2.53
mA
Volts
Volts
mV
mV
Volts
Volts
Volts
DIGITAL INPUTS
Input Voltage (CMOS)
Logic Levels (VIH) "1"
+4 — — Volts
Logic Level (VIL) "0"
— — +1 Volts
Input Current (@VIH=+DVS)"1"
5 µA
(@VIL=0) "0"
——
5 µA
Clock Pulse Width TPW1
25 — — ns
(A/D CLK) TPW0
25 — — ns
DIGITAL OUTPUTS
Output Data
Output Voltage
Output Current 
Logic Level "1"
Logic Level "0"
Output Current 
Logic Level "1"
Logic Level "0"
Output Data Delay, Td
8-bit Binary Parallel
3-State TTL compatible
–1.1 —
+3.7 —
— — 16
— — 16
— 18 30
mA
mA
µA
µA
ns
PERFORMANCE
Resolution
Maximum Sampling Rate
Minimum Sampling Rate
Aperature Delay, TA
Aperature Jitter
Differential Linearity Error
Integral Linearity Error
Differential Gain Error ‘
Differential Phase Error ‘
Footnotes:
ΠSee Technical Note 4
 Short VRB (pin 23) to VRBS (pin 22).
Short VRT (pin 17) to VRTS (pin 16).
Ž Short VRB (pin 23) to A GND.
Short VRT (pin 17) to VRTS (pin 16).
8 — — Bit
20 — — MHz
— — 0.5 MHz
— 4 — ns
— 30 — ps
— ±0.3 ±0.5 LSB
— +0.5 +1.3 LSB
— 1 —%
— 0.5 — deg
 OE=OV, VOH=+DVS–0.5V,
VOL=+0.4V
 OE=+DVS, VOH=+DVS, VOL=0V
‘ NTSC 40IRE mode ramp, 14.3MHz
sampling
POWER REQUIREMENTS MIN.
Power Supply (+AVS, +DVS)
I A GND - D GND I
Power Supply Current
Power Dissipation
+4.75
PHYSICAL/ENVIRONMENTAL
Operating Temp. Range
Storage Temp. Range
Package Type
ADC-305-1
ADC-305-3
Weight
ADC-305-1
ADC-305-3
TYP.
+5.0
12
60
MAX.
+5.25
100
17
85
–40 to +85°C
–55 to +150°C
24-pin Plastic DIP
24-pin Plastic SOP
2.0 grams
0.3 grams
UNITS
Volts
mV
mA
mW
TECHNICAL NOTES
1. The ADC-305 has separate +AVS and +DVS pins. It is
recommended that both +AVS and +DVS be powered from a
single supply since a time lag between start up of separate
supplies could induce latch up. Other external logic circuits
must be powered from a separate digital supply. +DVS (pins
11 and 13) and +AVs (pins 14, 15 and 18) should be tied
together externally. DGND (pins 2 and 24) and AGND (pins
20 and 21) should also be tied together externally. Power
supply grounds must be connected at one point to the
ground plane directly beneath the device. Digital returns
should not flow through analog grounds.
2. Bypass all power lines to ground with a 0.1µF ceramic chip
capacitor in parallel with a 47µF electrolytic capacitor.
Locate the bypass capacitor as close to the unit as
possible.
3. Even though the analog input capacitance is a low 15pF, it
is recommended that high frequency input be provided via
a high speed buffer amplifier. A parasitic oscillation may be
generated when a high speed amplifier is used. A 75 ohm
resister inserted between the output of an amplifier and the
analog input of the ADC-305 will improve the situation. A
resistor larger than 100 ohms may degrade linearity.
4. The input voltage range is determined by voltages applied
to VRB (Reference Bottom) and VRT (Reference Top). Keep
to the following equations;
0VVRBVRT2.8V
1.8VVRT–VRB2.8V
The analog input range is normally 2Vp-p.
Self Bias Mode
a. Tie VRB to VRBS, and tie VRT to VRTS respectively. The analog
input range in this case is +0.64V to +2.73V nominal.
b. Tie VRB to AGND, and tie VRT to VRTS respectively. The
analog input voltage range is 0 to +2.39V in this case.
Table 1. Digital Output Coding
STEP
DATA BITS OUT
VIN
CODE
DEC HEX MSB
LSB
OV Zero
0 00 0 0 0 0 0 0 0 0
+0.9922V +1/2FS –1LSB 127 7F 0 1 1 1 1 1 1 1
+1.000V
+1/2FS
128 80 1 0 0 0 0 0 0 0
+1.9922V
+FS
255 FF 1 1 1 1 1 1 1 1
2




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