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PDF AD9229 Data sheet ( Hoja de datos )
| Número de pieza | AD9229 | |
| Descripción | Quad 12-Bit 50/65 MSPS Serial LVDS 3V A/D Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
Four ADCs in 1 package
Serial LVDS digital output data rates
to 780 Mbps (ANSI-644)
Data and frame clock outputs
SNR = 69.5 dB (to Nyquist)
Excellent linearity
DNL = ±0.3 LSB (typical)
INL = ±0.4 LSB (typical)
400 MHz full power analog bandwidth
Power dissipation
1,350 mW at 65 MSPS
985 mW at 50 MSPS
1 V p-p to 2 V p-p input voltage range
3.0 V supply operation
Power-down mode
Digital test pattern enable for timing alignments
APPLICATIONS
Digital beam-forming systems for ultrasound
Wireless and wired broadband communications
Communication test equipment
GENERAL DESCRIPTION
The AD9229 is a quad, 12-bit, 65 MSPS analog-to-digital
converter (ADC) with an on-chip sample-and-hold circuit that
is designed for low cost, low power, small size, and ease of use.
The product operates at up to a 65 MSPS conversion rate and is
optimized for outstanding dynamic performance in applications
where a small package size is critical.
The ADC requires a single 3 V power supply and TTL-/CMOS-
compatible sample rate clock for full performance operation.
No external reference or driver components are required for
many applications.
The ADC automatically multiplies the sample rate clock for the
appropriate LVDS serial data rate. A data clock (DCO) for
capturing data on the output and a frame clock (FCO) trigger
for signaling a new output byte are provided. Power-down is
supported and typically consumes 3 mW when enabled.
Fabricated with an advanced CMOS process, the AD9229 is
available in a Pb-free, 48-lead LFCSP package. It is specified
over the industrial temperature range of –40°C to +85°C.
Quad, 12-Bit, 50/65 MSPS,
Serial, LVDS, 3 V A/D Converter
AD9229
VIN+A
VIN–A
VIN+B
VIN–B
VIN+C
VIN–C
VIN+D
VIN–D
FUNCTIONAL BLOCK DIAGRAM
PDWN DTP
DRVDD DRGND
AD9229
SHA
PIPELINE 12 SERIAL
ADC
LVDS
D+A
D–A
SHA
PIPELINE 12 SERIAL
ADC
LVDS
D+B
D–B
SHA
PIPELINE 12 SERIAL
ADC
LVDS
D+C
D–C
SHA
PIPELINE 12 SERIAL
ADC
LVDS
D+D
D–D
VREF
SENSE
REFT
REFB
REF
SELECT
0.5V
DATA RATE
MULTIPLIER
FCO+
FCO–
DCO+
DCO–
AGND LVDSBIAS
Figure 1.
CLK
PRODUCT HIGHLIGHTS
1. Four ADCs are contained in a small, space-saving package.
2. A data clock out (DCO) is provided, which operates up to
390 MHz and supports double-data rate operation (DDR).
3. The outputs of each ADC are serialized LVDS with data
rates up to 780 Mbps (12 bits × 65 MSPS).
4. The AD9229 operates from a single 3.0 V power supply.
5. Packaged in a Pb-free, 48-lead LFCSP package.
6. The internal clock duty cycle stabilizer maintains
performance over a wide range of input clock duty cycles.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 © 2005–2010 Analog Devices, Inc. All rights reserved.
1 page  
AD9229
AC SPECIFICATIONS
AVDD = 3.0 V, DRVDD = 3.0 V, maximum conversion rate, 2 V p-p differential input, 1.0 V internal reference, AIN = –0.5 dBFS, unless
otherwise noted.
Table 2.
Parameter
SIGNAL-TO-NOISE RATIO (SNR)
SIGNAL-TO-NOISE RATIO (SINAD)
EFFECTIVE NUMBER OF BITS
(ENOB)
SPURIOUS-FREE DYNAMIC RANGE
(SFDR)
WORST HARMONIC
(Second or Third)
WORST OTHER
(Excluding Second or Third)
TWO-TONE INTERMODULATION
DISTORTION (IMD)
AIN1 and AIN2 = –7.0 dBFS
fIN = 2.4 MHz
fIN = 10.3 MHz
fIN = 25 MHz
fIN = 30 MHz
fIN = 70 MHz
fIN = 2.4 MHz
fIN = 10.3 MHz
fIN = 25 MHz
fIN = 30 MHz
fIN = 70 MHz
fIN = 2.4 MHz
fIN = 10.3 MHz
fIN = 25 MHz
fIN = 30 MHz
fIN = 70 MHz
fIN = 2.4 MHz
fIN = 10.3 MHz
fIN = 25 MHz
fIN = 30 MHz
fIN = 70 MHz
fIN = 2.4 MHz
fIN = 10.3 MHz
fIN = 25 MHz
fIN = 30 MHz
fIN = 70 MHz
fIN = 2.4 MHz
fIN = 10.3 MHz
fIN = 25 MHz
fIN = 30 MHz
fIN = 70 MHz
fIN1 = 15 MHz
fIN2 = 16 MHz
fIN1 = 69 MHz
fIN2 = 70 MHz
Temperature
Full
25°C
Full
Full
25°C
Full
25°C
Full
Full
25°C
Full
Test
Level
IV
V
VI
VI
V
V
V
VI
VI
V
V
25°C V
Full VI
Full VI
25°C V
Full V
25°C V
Full VI
Full VI
25°C V
Full V
25°C V
Full VI
Full VI
25°C V
Full V
25°C V
Full VI
Full VI
25°C V
25°C V
AD9229-50
AD9229-65
Min Typ Max Min Typ Max Unit
69.5 70.4
69.0 70.2
dB
70.4 70.2 dB
68.7 69.6
dB
68.0 69.5
dB
67.2 67.1 dB
70.0 69.8 dB
70.0 69.8 dB
68.4 69.4
dB
67.3 69.0
dB
66.8 66.7 dB
11.3 11.3 Bits
11.3
11.1 11.2
10.8
85
11.3
10.9 11.2
10.8
85
Bits
Bits
Bits
Bits
dBc
85 85 dBc
76 85
dBc
73 85
dBc
78 77 dBc
–85 –85 dBc
–85 –85 dBc
–85 –76
dBc
–85 –73 dBc
–78 –77 dBc
–90 –90 dBc
–90 –90 dBc
–88 –81.7
dBc
–88 –79.7 dBc
–85 –83 dBc
–73 –73 dBc
25°C V
–68.5
–68.5
dBc
Rev. B | Page 4 of 40
5 Page 
AD9229
EQUIVALENT CIRCUITS
AVDD
VIN+, VIN–
AGND
Figure 4. Equivalent Analog Input Circuit
AVDD
CLK
170Ω
AGND
Figure 5. Equivalent Clock Input Circuit
AVDD
PDWN
375Ω
AGND
Figure 6. Equivalent Digital Input Circuit
DRVDD
VV
D– D+
VV
DRGND
Figure 7. Equivalent Digital Output Circuit
AVDD
DTP
375Ω
100kΩ
AGND
Figure 8. Equivalent DTP Input Circuit
Rev. B | Page 10 of 40
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9229.PDF ] | |
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