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AD9066 반도체 회로 부품 판매점

Dual 6-Bit/ 60 MSPS Monolithic A/D Converter



Analog Devices 로고
Analog Devices
AD9066 데이터시트, 핀배열, 회로
a
FEATURES
Two Matched ADCs on Single Chip
CMOS-Compatible I/O
Low-Power (400 mW) Dissipation
Single +5 V Supply
On-Chip Voltage Reference
Self-Biased for AC-Coupled Inputs
28-Lead SOIC and SSOP Packages
APPLICATIONS
Direct Broadcast Satellite (DBS) Receivers
QAM Demodulators
Wireless LANs
VSAT Receivers
Dual 6-Bit, 60 MSPS
Monolithic A/D Converter
AD9066
FUNCTIONAL BLOCK DIAGRAM
+VS
AD9066
VT
INA
6-BIT
DAC
D0A-D5A
REF A
ENCODE
INB
6-BIT
DAC
D0B-D5B
REF B
VB
PRODUCT DESCRIPTION
The AD9066 is a dual 6-bit ADC that has been optimized for
low-cost in-phase and quadrature (I and Q) demodulators.
Primary applications include digital direct broadcast satellite
applications where broadband quadrature phase shift keying
(QPSK) modulation is used. In these receivers the recovered signal
is separated into I and Q vector components and digitized.
To reduce total system cost and power dissipation, the AD9066
provides an internal voltage reference and operates from a
single +5 volt power supply. Digital outputs are CMOS com-
patible and rated to 60 MSPS conversion rates. The digital
input (ENCODE) utilizes a CMOS input stage with a TTL
compatible (1.4 V) threshold.
The AD9066 is housed in a 28-lead SOIC and a 28-lead SSOP
package and is available in two temperature grades. The
AD9066JR is rated for operation over the 0°C to 70°C commer-
cial temperature range. The AD9066AR/ARS is rated for the
–40°C to +85°C industrial temperature range.
The internal voltage reference insures that the analog input is
biased to midscale with low offset when driven from an ac-
coupled source. In dc-coupled applications, the midscale voltage
reference can be used to control external biasing amplifiers to
minimize offsets due to variations in temperature or supply voltage.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
PIN CONFIGURATIONS
ENCODE 1
28 D5A (MSB)
+VS 2
GND 3
27 D4A
26 D3A
GND 4
25 D2A
+VS 5
INA 6
AD9066
(JR/AR)
24 D1A
23 D0A (LSB)
GND 7 TOP VIEW 22 GND
+VS 8 (Not to Scale) 21 +VS
VT 9
20 D5B (MSB)
REF A 10
19 D4B
INB 11
18 D3B
REF B 12
17 D2B
VB 13
16 D1B
NC 14
15 D0B (LSB)
NC = NO CONNECT
+VS 1
28 GND
VT 2
27 INA
REF A 3
INB 4
26 +VS
25 GND
REF B 5
24 GND
VB 6
AD9066
(ARS)
23 +VS
NC 7 TOP VIEW 22 ENCODE
(LSB) D0B 8 (Not to Scale) 21 D5A (MSB)
D1B 9
20 D4A
D2B 10
19 D3A
D3B 11
18 D2A
D4B 12
17 D1A
(MSB) D5B 13
16 D0A (LSB)
+VS 14
15 GND
NC = NO CONNECT
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000


AD9066 데이터시트, 핀배열, 회로
AD9066–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (+VS = +5 V, AIN = 15.5 MHz, Encode Rate = 60 MSPS, TC = TA)
Parameter
Test
Level Temp
AD9066JR
Min Typ
Max
AD9066AR/ARS
Min Typ
Max Unit
ANALOG INPUT
Full-Scale Input Range
Gain Matching (FS Range)
DC Input (Midscale)1
Input Offset1
Input Capacitance
Input Resistance (DC)
Input Bandwidth (3 dB)
Gain Flatness (to 15 MHz)
Integral Linearity
Differential Linearity
Monotonicity
VI Full
475 500
525 450 500
530 mV
IV Full
16
16 mV
V +25°C
+VS – 1.1
+VS – 1.1
V
VI Full
–1.0
+1.0 –1.0
+1.0 LSBs
IV Full
10 15
10 15 pF
VI Full
25 45
55 22 45
57 k
V +25°C
100
100 MHz
V +25°C
0.25
0.25 dB
VI Full
–1.0
+1.0 –1.0
+1.0 LSBs
VI Full
–0.5
+0.5 –0.5
+0.5 LSBs
VI Full
Guaranteed
Guaranteed
SWITCHING PERFORMANCE
Max Conversion Rate
Output Delay (tV)2
Output Delay (tPD)2
Aperture Uncertainty (Jitter)
Aperture Time (tA)
DYNAMIC PERFORMANCE3
Effective Number of Bits
SINAD
Harmonic Distortion (THD)
Crosstalk Rejection
VI Full
60
IV Full
4
IV Full
V +25°C
10
V +25°C
1.0
VI +25°C 5.3 5.7
VI +25°C 34 36
VI +25°C 40 50
IV +25°C 40 50
60
4
11
10
1.0
5.2 5.7
33 36
40 50
40 50
MSPS
ns
12 ns
ps rms
ns
Bits
dB
dB
dBc
ENCODE INPUT
Logic High Voltage
Logic Low Voltage
Input High Current
Input Low Current
Pulsewidth High
Pulsewidth Low
VI Full
VI Full
VI Full
VI Full
IV Full
IV Full
2.0
7.0
7.0
2.0
0.8
500
500
7.0
7.0
V
0.8 V
500 µA
500 µA
ns
ns
DIGITAL OUTPUTS
Output Coding
Logic High Voltage (IOH = 1 mA)
Logic Low Voltage (IOL = 1 mA)
POWER SUPPLY
+VS Supply Voltage
Power Supply Rejection Ratio1
+VS Supply Current
Power Dissipation4
Full
VI Full
VI Full
VI Full
IV Full
VI Full
VI Full
Offset Binary
3.8
0.4
4.75
110
80
400
5.25
130
120
600
Offset Binary
3.8
0.4
V
V
4.75
110
80
400
5.25 V
130 mV/V
120 mA
600 mW
NOTES
1For ac coupled applications, the ADC is internally biased to insure that the midpoint transition of the ADC is within the limits specified with no signal applied. For
dc coupled applications, the dc value of the midpoint transition voltage will track the supply voltage within the limits shown for dc input (midscale) plus the dc offset.
Power Supply Rejection Ratio (PSRR) refers to the variation of the input signal range (gain) to supply voltage.
2tV and tPD are measured from the 1.4 V level of the Clock and the 50% level between VOH and VOL. The ac load on all the digital outputs during test is 10 pF (max),
the dc load will not exceed ± 40 µA.
3Effective number of bits (ENOB) and THD are measured using a FFT with a pure sine wave analog input @ 15.5 MHz, 1 dB below full scale. ENOB is calculated by
ENOB = (SNR – 1.76 dB)/6.02; THD is measured from full scale to the sum of the second through seventh harmonic of the input.
4Typical thermal impedance for the “R” style (SOIC) 28-lead package is: θJC = 4°C/W, θCA = 41°C/W, θJA = 45°C/W, and the “RS” style (SSOP) 28-lead package is:
θJC = 26.97°C/W, θCA = 51.61°C/W, θJA = 78.58°C/W.
Specifications subject to change without notice.
–2– REV. A




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