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PDF AD6644 Data sheet ( Hoja de datos )
| Número de pieza | AD6644 | |
| Descripción | 40 MSPS/65 MSPS Analog-to-Digital Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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14-Bit, 40 MSPS/65 MSPS
Analog-to-Digital Converter
AD6644
FEATURES
65 MSPS guaranteed sample rate
40 MSPS version available
Sampling jitter < 300 fs
100 dB multitone SFDR
1.3 W power dissipation
Differential analog inputs
Pin compatible to AD6645
Twos complement digital output format
3.3 V CMOS compatible
Data-ready for output latching
APPLICATIONS
Multichannel, multimode receivers
AMPS, IS-136, CDMA, GSM, WCDMA
Single channel digital receivers
Antenna array processing
Communications instrumentation
Radar, infrared imaging
Instrumentation
GENERAL DESCRIPTION
The AD6644 is a high speed, high performance, monolithic 14-bit
analog-to-digital converter (ADC). All necessary functions,
including track-and-hold (TH) and reference, are included on-
chip to provide a complete conversion solution. The AD6644
provides CMOS-compatible digital outputs. It is the third
generation in a wideband ADC family, preceded by the AD9042
(12-bit 41 MSPS) and the AD6640 (12-bit 65 MSPS, IF
sampling).
Designed for multichannel, multimode receivers, the AD6644
is part of the Analog Devices, Inc. new SoftCell® transceiver
chipset. The AD6644 achieves 100 dB multitone, spurious-free
dynamic range (SFDR) through the Nyquist band. This break-
through performance eases the burden placed on multimode
digital receivers (software radios) which are typically limited by
the ADC. Noise performance is exceptional; typical signal-to-
noise ratio is 74 dB.
The AD6644 is also useful in single channel digital receivers
designed for use in wide-channel bandwidth systems (CDMA,
WCDMA). With oversampling, harmonics can be placed
outside the analysis bandwidth. Oversampling also facilitates
the use of decimation receivers (such as the AD6620), allowing
the noise floor in the analysis bandwidth to be reduced. By
replacing traditional analog filters with predictable digital
components, modern receivers can be built using fewer RF
components, resulting in decreased manufacturing costs, higher
manufacturing yields, and improved reliability.
The AD6644 is built on the Analog Devices high speed
complementary bipolar process (XFCB) and uses an innovative,
multipass circuit architecture. Units are packaged in a 52-lead
plastic low profile quad flat package (LQFP) specified from –
25°C to +85°C.
PRODUCT HIGHLIGHTS
1. Guaranteed sample rate is 65 MSPS.
2. Fully differential analog input stage.
3. Digital outputs can be run on 3.3 V supply for easy interface
to digital ASICs.
4. Complete solution: reference and track-and-hold.
5. Packaged in small, surface-mount, plastic, 52-lead LQFP.
AVCC DVCC
FUNCTIONAL BLOCK DIAGRAM
AIN A1 TH1
AIN
VREF
2.4V
ENCODE
ENCODE
INTERNAL
TIMING
TH2
A2 TH3
TH4
TH5 ADC3
ADC1 DAC1
5
ADC2 DAC2
5
DIGITAL ERROR CORRECTION LOGIC
AD6644
6
GND
DMID OVR DRY D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
(MSB)
(LSB)
Figure 1.
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.
1 page  
AD6644
DIGITAL SPECIFICATIONS
AVCC = 5 V, DVCC = 3.3 V; TMIN = −25°C, TMAX = +85°C, unless otherwise noted.
Table 2.
Parameter
ENCODE INPUTS (ENCODE, ENCODE)
Differential Input Voltage2
Differential Input Resistance
Differential Input Capacitance
LOGIC OUTPUTS (D13 to D0, DRY, OVR)
Logic Compatibility
Logic 1 Voltage3
Logic 0 Voltage3
Output Coding
DMID
Temp
Test Level1
AD6644AST-40
Min Typ
Max
AD6644AST-65
Min Typ
Max
Unit
Full
25°C
25°C
IV
V
V
0.4
10
2.5
0.4
10
2.5
V p-p
kΩ
pF
Full V
Full V
Full V
CMOS
2.5
0.4
Twos complement
DVCC/2
CMOS
2.5
0.4
Twos complement
DVCC/2
V
V
V
1 See the Explanation of Test Levels section.
2 All ac specifications tested by driving ENCODE and ENCODE differentially. Reference Figure 18 for performance vs. encode power.
3 Digital output logic levels: DVCC = 3.3 V, CLOAD = 10 pF. Capacitive loads >10 pF degrade performance.
SWITCHING SPECIFICATIONS
AVCC = 5 V, DVCC = 3.3 V; ENCODE and ENCODE = maximum conversion rate MSPS; TMIN = –25°C, TMAX = +85°C, unless otherwise noted.
Table 3.
Parameter
Maximum Conversion Rate
Minimum Conversion Rate
ENCODE Pulse Width High
ENCODE Pulse Width Low
Temp
Full
Full
Full
Full
Test Level1
II
IV
IV
IV
AD6644AST-40
Min Typ Max
40
15
10
10
AD6644AST-65
Min Typ Max
65
15
6.5
6.5
Unit
MSPS
MSPS
ns
ns
1 See the Explanation of Test Levels section.
AVCC = 5 V, DVCC = 3.3 V; ENCODE and ENCODE = maximum conversion rate MSPS; TMIN = −25°C, TMAX = +85°C, CLOAD = 10 Pf,
unless otherwise noted.
Table 4.
Parameter
ENCODE INPUT PARAMETERS2
Encode Period @ 65 MSPS
Encode Period @ 40 MSPS
Encode Pulse Width High3 @ 65 MSPS
Encode Pulse Width Low @ 65 MSPS
ENCODE/DATA READY
Encode Rising to Data Ready Falling
Encode Rising to Data Ready Rising
@ 65 MSPS (50% Duty Cycle)
@ 40 MSPS (50% Duty Cycle)
ENCODE/DATA (D13:0), OVR
ENCODE to DATA Falling Low
ENCODE to DATA Rising Low
ENCODE to DATA Delay (Hold Time)4
ENCODE to DATA Delay (Setup Time)5
Encode = 65 MSPS (50% Duty Cycle)
Encode = 40 MSPS (50% Duty Cycle)
Name
tENC
tENC
tENCH
tENCL
tDR
tE_DR
tE_FL
tE_RL
tH_E
tS_E
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Test Level1
V
V
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
AD6644AST-40/65
Min Typ Max
Unit
15.4 ns
25 ns
6.2 7.7 9.2 ns
6.2 7.7 9.2 ns
2.6 3.4 4.6 ns
tENCH + tDR
10.3 11.1 12.3 ns
15.1 15.9 17.1 ns
3.8 5.5 9.2 ns
3.0 4.3 6.4 ns
3.0 4.3 6.4 ns
tENC − tE_FL
6.2 9.8 11.6 ns
15.9 19.4 21.2 ns
Rev. D | Page 4 of 24
5 Page 
AD6644
100
95 WORST OTHER SPUR
90
ENCODE = 65MSPS
AIN = –1dBFS
85
80
75
70
HARMONICS (SECOND, THIRD)
65
60
55
0 10 20 30 40 50 60 70 80 90 100
ANALOG FREQUENCY (MHz)
Figure 10. Harmonics vs. Analog Frequency (IF)
120
110
100
90
80
70
60
50
40
30
20
10
0
–80
ENCODE = 65MSPS
AIN = 15.5MHz
dBFS
dBc
SFDR = 90dB
REFERENCE LINE
–70 –60 –50 –40 –30 –20 –10
ANALOG INPUT POWER LEVEL (dBFS)
0
Figure 11. Single-Tone SFDR
0
ENCODE = 65MSPS
–10 AIN = 19MHz,
–20 19.5MHz @ –7dBFS
NO DITHER
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
0
5 10 15 20
FREQUENCY (MHz)
25
30
Figure 12. Two Tones at 19 MHz and 19.5 MHz
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
0
ENCODE = 65MSPS
AIN = 15MHz,
15.5MHz @ –7dBFS
NO DITHER
5 10 15 20 25 30
FREQUENCY (MHz)
Figure 13. Two Tones at 15 MHz and 15.5 MHz
110
dBFS
100
90 ENCODE = 65MSPS
F1 = 15MHz
80 F2 = 15.5MHz
70
dBc
60
50
SFDR = 90dB
REFERENCE LINE
40
30
20
10
0
–77 –67 –57 –47 –37 –27 –17
INPUT POWER LEVEL [(F1 = F2) dBFS]
–7
Figure 14. Two-Tone SFDR
100
95
90
85
80
75
70
65
60
0
AIN = 2.2MHz @ –1dBFS
WORST SPUR
SNR
10 20 30 40 50 60 70 80
ENCODE FREQUENCY (MHz)
Figure 15. SNR, Worst Spurious vs. Encode
90
Rev. D | Page 10 of 24
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet AD6644.PDF ] | |
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