AD9226 판매점 - ADC Converter

AD9226 반도체 회로 부품 판매점

ADC Converter

Analog Devices

Complete 12-Bit, 65 MSPS

ADC Converter

AD9226

FEATURES

Signal-to-Noise Ratio: 69 dB @ fIN = 31 MHz

Spurious-Free Dynamic Range: 85 dB @ fIN = 31 MHz

Intermodulation Distortion of –75 dBFS @ fIN = 140 MHz

ENOB = 11.1 @ fIN = 10 MHz

Low-Power Dissipation: 475 mW

No Missing Codes Guaranteed

Differential Nonlinearity Error: ؎0.6 LSB

Integral Nonlinearity Error: ؎0.6 LSB

Clock Duty Cycle Stabilizer

Patented On-Chip Sample-and-Hold with

Full Power Bandwidth of 750 MHz

Straight Binary or Two’s Complement Output Data

28-Lead SSOP, 48-Lead LQFP

Single 5 V Analog Supply, 3 V/5 V Driver Supply

Pin-Compatible to AD9220, AD9221, AD9223,

AD9224, AD9225

FUNCTIONAL BLOCK DIAGRAM

CLK

AVDD

DRVDD

VINA

VINB

CAPT

CAPB

VREF

SENSE

DUTY CYCLE STABILIZER

SHA

MDAC1

8-STAGE

1-1/2-BIT PIPELINE

A/D

A/D 4

CALIBRATION

ROM

CORRECTION LOGIC

OUTPUT BUFFERS

REF 1V

SELECT

MODE

SELECT

AD9226

REFCOM MODE

AVSS DRVSS

OTR

BIT 1

(MSB)

BIT 12

(LSB)

PRODUCT DESCRIPTION

The AD9226 is a monolithic, single-supply, 12-bit, 65 MSPS

analog-to-digital converter with an on-chip, high-performance

sample-and-hold amplifier and voltage reference. The AD9226

uses a multistage differential pipelined architecture with a pat-

ented input stage and output error correction logic to provide

12-bit accuracy at 65 MSPS data rates. There are no missing

codes over the full operating temperature range (guaranteed).

The input of the AD9226 allows for easy interfacing to both

imaging and communications systems. With a truly differential

input structure, the user can select a variety of input ranges and

offsets including single-ended applications.

The sample-and-hold amplifier (SHA) is well suited for IF

undersampling schemes such as in single-channel communi-

cation applications with input frequencies up to and well

beyond Nyquist frequencies.

The AD9226 has an on-board programmable reference. For sys-

tem design flexibility, an external reference can also be chosen.

A single clock input is used to control all internal conversion

cycles. An out-of-range signal indicates an overflow condition

that can be used with the most significant bit to determine low

or high overflow.

The AD9226 has two important mode functions. One will set

the data format to binary or two’s complement. The second will

make the ADC immune to clock duty cycle variations.

PRODUCT HIGHLIGHTS

IF Sampling—The patented SHA input can be configured for

either single-ended or differential inputs. It will maintain out-

standing AC performance up to input frequencies of 300 MHz.

Low Power—The AD9226 at 475 mW consumes a fraction of

the power presently available in existing, high-speed monolithic

solutions.

Out of Range (OTR)—The OTR output bit indicates when

the input signal is beyond the AD9226’s input range.

Single Supply—The AD9226 uses a single 5 V power supply

simplifying system power supply design. It also features a sepa-

rate digital output driver supply line to accommodate 3 V and

5 V logic families.

Pin Compatibility—The AD9226 is similar to the AD9220,

AD9221, AD9223, AD9224, and AD9225 ADCs.

Clock Duty Cycle Stabilizer—Makes conversion immune to

varying clock pulsewidths.

REV. B

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700 World Wide Web Site: http://www.analog.com

Fax: 781/326-8703

AD9226* Product Page Quick Links

Last Content Update: 11/01/2016

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Documentation

Application Notes

• AN-1142: Techniques for High Speed ADC PCB Layout

• AN-282: Fundamentals of Sampled Data Systems

• AN-302: Exploit Digital Advantages in an SSB Receiver

• AN-345: Grounding for Low-and-High-Frequency Circuits

• AN-348: Avoiding Passive-Component Pitfalls

• AN-501: Aperture Uncertainty and ADC System

Performance

• AN-715: A First Approach to IBIS Models: What They Are

and How They Are Generated

• AN-737: How ADIsimADC Models an ADC

• AN-741: Little Known Characteristics of Phase Noise

• AN-742: Frequency Domain Response of Switched-

Capacitor ADCs

• AN-756: Sampled Systems and the Effects of Clock Phase

Noise and Jitter

• AN-807: Multicarrier WCDMA Feasibility

• AN-808: Multicarrier CDMA2000 Feasibility

• AN-827: A Resonant Approach to Interfacing Amplifiers to

Switched-Capacitor ADCs

• AN-835: Understanding High Speed ADC Testing and

Evaluation

• AN-905: Visual Analog Converter Evaluation Tool Version

1.0 User Manual

• AN-935: Designing an ADC Transformer-Coupled Front

End

Data Sheet

• AD9226: Complete 12-Bit, 65 MSPS ADC Converter Data

Sheet

User Guides

• UG-173: High Speed ADC USB FIFO Evaluation Kit

(HSC-ADC-EVALB-DCZ)

Tools and Simulations

• Visual Analog

Reference Materials

Technical Articles

• Correlating High-Speed ADC Performance to Multicarrier

3G Requirements

• DNL and Some of its Effects on Converter Performance

• MS-2210: Designing Power Supplies for High Speed ADC

Design Resources

• AD9226 Material Declaration

• PCN-PDN Information

• Quality And Reliability

• Symbols and Footprints

Discussions

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Sample and Buy

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Technical Support

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number

* This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet. Note: Dynamic changes to

the content on this page does not constitute a change to the revision number of the product data sheet. This content may be

frequently modified.

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AD9226 반도체 회로 부품 판매점

ADC Converter

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