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PDF SH66K31C Data sheet ( Hoja de datos )
| Número de pieza | SH66K31C | |
| Descripción | Mask 4-bit Microcontroller | |
| Fabricantes | Sino Wealth | |
| Logotipo |  |
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SH66K31C
Mask 4-bit Micro-controller
Features
SH6610C-based single-chip 4-bit micro-controller
ROM: 1024 X 16 bits
RAM:
- 32 X 4 bits System Register
- 48 X 4 bits data memory
Operation Voltage:
- VDD = 1.8V - 3.6V
- VDD = VLPD - 3.6V (LPD enable)
14 CMOS bi-directional I/O pins
4-level Stack (including interrupts)
One 8-bit auto re-loaded timer/counter
Warm-up timer
Powerful interrupt sources:
- Timer0 interrupt
- External interrupts: PORTA / B /C (Falling edge)
Oscillator (code option)
- Ceramic resonator: 400kHz - 4MHz
- External input clock: 400kHz - 4MHz
Instruction cycle time:
- 4/fOSC
- 16/fOSC
Two low power operation modes: HALT and STOP
Reset
- Built-in power-on reset (POR)
Built-in Pull-high resistor for reset pin (code option)
Built-in remote control carrier synthesizer by software
option
Port interrupt source selection (code option)
Chip form or 20-pin DIP/ TSSOP package
General Description
SH66K31C is a single-chip 4-bit micro-controller. This device integrates an SH6610C CPU core, RAM, ROM, timer, and
programmable input/output driving buffers and carrier synthesizer. The standby function, which can be used to stop/start the
ceramic resonator oscillation, facilitates the low power dissipation of the system. The SH66K31C is suitable for infrared remote
control transmitter application.
Pin Configuration
PORTC.2
PORTC.3
PORTD.0
PORTD.1
REM
VDD
OSCO
OSCI
GND
RESET
1
2
3
4
5
6
7
8
9
10
20 PORTC.1
19 PORTC.0
18 PORTB.3
17 PORTB.2
16 PORTB.1
15 PORTB.0
14 PORTA.3
13 PORTA.2
12 PORTA.1
11 PORTA.0 / T0
1 V2.0
1 page  
SH66K31C
2.2. Configuration of System Register
Address Bit3 Bit2 Bit1 Bit0 R/W
Remarks
$00 - IET0 - IEP R/W Interrupt enable flags
$01
- IRQT0 -
IRQP
R/W Interrupt request flags
$02
-
TM0.2 TM0.1 TM0.0
R/W Timer0 mode register (Prescaler)
$03 - - - - - Reserved
$04
TL0.3
TL0.2
TL0.1
TL0.0
R/W Timer0 load/counter register low nibble
$05
TH0.3
TH0.2
TH0.1
TH0.0
R/W Timer0 load/counter register high nibble
$06 - - - - - Reserved
$07 - - - - - Reserved
$08
PA.3
PA.2
PA.1
PA.0
R/W PORTA
$09
PB.3
PB.2
PB.1
PB.0
R/W PORTB
$0A
PC.3
PC.2
PC.1
PC.0
R/W PORTC
$0B -
-
PD.1
PD.0
R/W PORTD
$0C - - - - - Reserved
$0D -
-
-
REMO
R/W REM data output
$0E
TBR.3 TBR.2 TBR.1 TBR.0
R/W Table Branch Register
$0F
INX.3
INX.2
INX.1
INX.0
R/W Pseudo index register
$10
DPL.3 DPL.2 DPL.1 DPL.0
R/W Data pointer for INX low nibble
$11
-
DPM.2 DPM.1 DPM.0
R/W Data pointer for INX middle nibble
$12
-
DPH.2 DPH.1 DPH.0
R/W Data pointer for INX high nibble
$13 PULLEN CPS CF1 CF0
Bit1 - 0: Carrier frequency control
W Bit2: Carrier OSC pre-divider
Bit3: Port pull-high resistor control
$14 - - - - - Reserved
LPD enable control (LPD3 - 0):
$15
LPD3
LPD2
LPD1
LPD0
W 0101: LPD enable (Power-on initial)
1010: LPD disable
$16 PACR.3 PACR.2 PACR.1 PACR.0 W Set PORTA to be output control
$17 PBCR.3 PBCR.2 PBCR.1 PBCR.0 W Set PORTB to be output control
$18 PCCR.3 PCCR.2 PCCR.1 PCCR.0 W Set PORTC to be output control
$19 -
- PDCR.1 PDCR.0 W Set PORTD to be output control
$1A - - - - - Reserved
$1B -
$1C -
$1D -
- - - - Reserved
-
T0S T0E
W
Bit0: T0 signal edge
Bit1: T0 signal source
- - - - Reserved
$1E - - - - - Reserved
$1F - - - - - Reserved
*Please refer to SH6610C user’s manual for more detailed information on System Register.
5
5 Page 
SH66K31C
Port Interrupt
When opt_pint is “0” (Default), PORTB.0 - 3, PORTC.0 - 3 are used as port interrupt sources. When opt_pint is “1”, PORTA.1 -
3,PORTB.0 - 3 and PORTC.0 are used as port interrupt sources. Since PORT I/O is a bit programmable I/O, only the transitions
from VDD to GND will generate an interrupt request. Thus, further falling edge transitions will not be able to make interrupt
request until all of the pins return to VDD PORT Interrupt Block Diagram.
IEP
PC.n
PB.n
PCCR.n
PBCR.n
Note: n=0, 1, 2, 3
Falling
Edge Detector
Port Interrupt
IRQP
opt_pint = 0 (Default)
IEP
PA.n
PC.0
PB.x
PACR.n
PCCR.0
PBCR.x
Note: n = 1, 2, 3
x = 0, 1, 2, 3
Falling
Edge Detector
Port Interrupt
IRQP
opt_pint = 1
Port interrupt PROGRAMMING NOTES：
If the user wants to generate an interrupt when a falling edge from VDD to GND emerges on the port, the following must be executed.
1. Set the port as input port, fill in the port data register with “1” and avoid port floating.
2. Pull-high the port (Use external pull-high resistance or set PULLEN to “1”).
And further falling edge transition would not be able to make interrupt request until all of the pins return to VDD
3. Set corresponding IEP to “1” and clear IRQP to “0”
11
11 Page | ||
| Páginas | Total 27 Páginas | |
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