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PDF SH6631A Data sheet ( Hoja de datos )
| Número de pieza | SH6631A | |
| Descripción | Mask 4-bit Microcontroller | |
| Fabricantes | Sino Wealth | |
| Logotipo |  |
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SH6631A
Mask 4-bit Microcontroller
Features
SH6610C-based single-chip 4-bit micro-controller
ROM: 1024 X 16 bits ROM
RAM: 48 X 4 bits RAM (Data Memory)
Operation voltage: 1.8V – 3.6V (Typically 3.0V)
14 CMOS bi-directional I/O pins
4-level subroutine nesting (including interrupts)
One 8-bit auto re-loadable timer/counter
Warm-up timer for power-on reset
Powerful interrupt sources:
- Internal interrupt (Timer0).
- External interrupts: PortB & PortC (Falling edge).
Built-in remote control carrier synthesizer FOSC/8 or
FOSC/12 by software option
Oscillator
Ceramic resonator: 400K - 4MHz.
Instruction cycle time:
- 4/455KHz ( ≈ 8.79µs) for 455KHz OSC clock
- 4/3.64MHz ( ≈ 1.1µs) for 3.64MHz OSC clock
Two low power operation modes: HALT and STOP
Pull-up resistor for reset pin (code option)
Port interrupt source select (code option)
General Description
SH6631A is dedicated to infrared remote control transmitter applications. This chip integrates the SH6610C 4-bit CPU core with
SRAM, program ROM, an 8-bit timer, and programmable input/output driving buffers and carrier synthesizer. The standby
function, which can be used to stop/start the ceramic resonator oscillation, facilitating the low power dissipation of the system.
Pin Configuration
PORTC.2
PORTC.3
PORTD.0
PORTD.1
REM
VDD
OSCO
OSCI
GND
RESET
1
2
3
4
5
6
7
8
9
10
20 PORTC.1
19 PORTC.0
18 PORTB.3
17 PORTB.2
16 PORTB.1
15 PORTB.0
14 PORTA.3
13 PORTA.2
12 PORTA.1
11 PORTA.0
1 V2.3
1 page  
SH6631A
4. Timer0
4.1. Configuration and Operation
Timer-0 consists of an 8-bit write-only timer load register
(TL0L, TL0H), and an 8-bit read-only timer counter (TC0L,
TC0H). The counter and load register both have low order
digits and high order digits. Writing data into the timer load
register (TL0L, TL0H) can initialize the timer counter.
Load register programming: Write the low-order digit first,
and then the high-order digit. The timer counter is
automatically loaded with the contents of the load register
when the high order digit is written or counter counts
overflow from $FF to $00.
Timer Load Register: Since register H controls the physical
READ/WRITE operations, follow the following rules:
Write Operation:
Low nibble first;
High nibble to update the counter
Read Operation:
High nibble first;
Followed by Low nibble.
Load Reg. L Load Reg. H
8-bit timer counter
Latch Reg. L
Figure. 1 Timer Load register Configure
4.2. Timer0 Interrupt
The timer overflow will generate an internal interrupt request when the counter counts overflow from $FF to $00. If the interrupt
enable flag is enabled, then a timer interrupt service routine will start. This can also be used to wake CPU from HALT mode.
5
5 Page 
SH6631A
8. Interrupt
Two interrupt sources are available on SH6631A:
-Timer0 overflow interrupt
-Port's falling edge detection interrupt ( PBC )
Interrupt Control Bits and Interrupt Service
The interrupt control flags are mapped on $00 through $01 of the system register. They can be accessed or tested by the
program. These flags are cleared to 0 at initialization by chip reset.
Address Bit3 Bit2 Bit1 Bit0
Remarks
$00
- IET0 -
IEP interrupt enable flags
$01
- IRQT0 -
IRQP interrupt request flags
When IEx is set to 1 and the interrupt request is generated (IRQx is 1) , the interrupt will be activated and vector address will be
generated from the priority PLA corresponding to the interrupt sources. When an interrupt occurs, the PC and CY flag will be
saved into stack memory and jump to interrupt service vector address. After the interrupt occurs, all interrupt enable flags (IEx)
are reset to 0 automatically, thus, when IRQx is 1 and IEx is set to 1 again, the interrupt will be activated and vector address will
be generated from the priority PLA corresponding to the interrupt sources.
Interrupt Servicing Sequence Diagram:
12345
Inst. cycle
Instruction
Execution
N
Instruction
Execution
I1
Instruction
Execution
I2
Interrupt Generated Interrupt Accepted
Vector Generated Fetch Vector address
Stacking
Reset IE.X
Start at vector
address
Interrupt Nesting:
During the SH6610C CPU interrupt service, the user can enable any interrupt enable flag before returning from the interrupt.
The servicing sequence diagram shows the next interrupt and the next nesting interrupt occurrences. If the interrupt request is
ready and the instruction of execution N is IE enable, then the interrupt will start immediately after the next two instruction
executions. However, if instruction I1 or instruction I2 disables the interrupt request or enable flag, then the interrupt service will
be terminated.
9. HALT and STOP mode
After the execution of HALT instruction, SH6631A will enter HALT mode. In HALT mode, the CPU will stop operating; however,
the peripheral circuit (timer) will keep operating.
After the execution of STOP instruction, SH6631A will enter STOP mode.
In STOP mode, the entire chip (including oscillator) will stop operating.
In HALT mode, SH6631A can be woken up if an interrupt occurs.
In STOP mode, SH6631A can be woken up if a port interrupt occurs.
10. Warm-up Timer
The SH6631A has a built in oscillator warm-up timer to eliminate unstable state of initial oscillation when oscillator starts
oscillating in the following conditions:
(1) Power-on reset
(2) Wake-up from STOP mode
The warm-up time interval (FOSC/512 cycles of oscillator) is a follows:
(1) Power-on reset interval is as long as the initial oscillator’s frequency mode warm-up timer interval.
When SH6631A operates in 455K Hz frequency, the warm-up time interval is 1.13 ms.
(2) 4MHz crystal oscillator wake-up:
When SH6631A operates in 4 MHz frequency, the warm-up time interval is 0.128 ms.
11
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| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet SH6631A.PDF ] | |
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