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PDF SH6614 Data sheet ( Hoja de datos )
| Número de pieza | SH6614 | |
| Descripción | 4K 4-Bit Microcontroller | |
| Fabricantes | Sino Wealth | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de SH6614 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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SH6614
SH6614B
SH6614C
4K 4-Bit Microcontroller with LCD Driver
Features
! SH6610C-based single-chip 4-bit microcontroller
! ROM: 4096 X 16 bits
! RAM: 512 X 4 bits
! Operation voltage: 2.4V – 6.0V
! 8 CMOS bi-directional I/O pins
! 4-Level subroutine nesting (include interrupts)
! One 8-bit auto re-load timer/counter
! Wem-up timer for power-on reset
! Powerful interrupt sources:
- External interrupts ( INT0 )
- Internal interrupt (Timer0)
- Internal interrupt (Base Timer)
- Port's falling edge interrupt: PORTB ( INT1 )
! 8-bit Base timer
! LCD driver:
240 dots (1/8 duty 1/4 bias) or 136 dots (1/4 duty 1/3 bias)
! LCD used as scan output
! Built-in dual tone PSG with one noise generator
! 2 Clock sources
OSC: (code option select crystal or RC type)
- Crystal oscillator 32.768K
- RC oscillator: 262K
OSCX: (system register selected ceramic or RC type)
- Ceramic oscillator 455K
- RC oscillator 1.8M or 2M
! Instruction cycle time:
- 122.07µs for 32.768 KHz crystal
- 15.27µs for 262 KHz RC
- 8.79µs for 455KHz ceramic
- 2.22µs for 1.8 MHz RC
- 2µs for 2.0 MHz RC
! Two low power operation modes: HALT and STOP
! Low power consumption
General Description
SH6614 (SH6614B, SH6614C) is a single chip microcontroller integrated with SRAM, timer and dual-tone PSG, LCD driver, and
I/O port. This chip builds in a dual-oscillator to enhance the total chip performance.
Pin Configuration
QFP64
R
ET
SSS
PPPPPP
S
E
EEE
A A B B B B V ENNN S V V V VGGG
2
3
0
1
2
3
D
D
T
CCC
T
4
3
2
1
1
2
3
PA1
PA0
OSCXI
OSCXO
GND
OSCO
OSCI
COM1
COM2
COM3
COM4
COM5
COM6
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
52
53
54
55
56
57
SH6614
58 SH6614B
59 SH6614C
60
61
62
63
64
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
32
31
30
29
28
27
26
25
24
23
22
21
20
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
CCS S S S S SNNNS S S S S S S S
OOE E E E E ECCC E E E E E E E E
MMGGGGGG
GGGGGGGG
78322222
22222111
098765
43210987
1 V2.2
1 page  
Pad Description
Pad No.
Designation
1, 2, 31 - 58
3-6
7
8
9
10 - 13
SEG1 - SEG30
V1 - V4
TEST
RESET
VDD
Port B.3 - Port B.0
14 - 17
Port A.3 - Port A.0
18
19
20
21
22
23 - 26
27 - 30
OSCXI
OSCXO
GND
OSCO
OSCI
COM1 - COM4
COM5 - COM8/SEG34 - SEG31
SH6614/B/C
I/O Description
O
Segment signal output for LCD display;
share with scan output
I Connected with external LCD divided resistance
I Test pin (Internal pull-low). No connection for user
I Reset input (No internal pull-up)
P Power supply
I/O Bit programmable I/O, Vector interrupt ( INT1 )
I/O Bit programmable I/O, PA.0 shared with INT0
PA.1, PA.2shared with PSG output
I Oscillator X input
O Oscillator X output
P Ground
O Oscillator output
I Oscillator input
O Common signal output for LCD display
O Common/segment signal output for LCD display
5
5 Page 
SH6614/B/C
7.2. Controlling the pull-up MOS
PORTA, PORTB contain pull-up MOS controlled by program. Bit3 of the PMOD register controls the on/off of all pull-up MOS
simultaneously. Pull-up MOS are also controlled by the port data registers (PA, PB) of each port as well. Thus the pull-up MOS
can be turned on/off.
7.3. Port Interrupt
PORTB interrupt (falling edge) is not controlled by the Port I/O register. This means that if a interrupt request (IEx is set to 1 &
one port bit high goes low) has been touched therefore the condition is the other port bits are high level whenever the port bit is
output or input.
7.4. External INT0
PortA.0 is shared by external interrupts (active low).
7.5. Port I/O control register:
Address
$0B
$0C
Bit3
PACR.3
PBCR.3
Bit2
PACR.2
PBCR.2
I/O control register: PACR.X, PBCR.X (X = 0, 1, 2, 3)
1: Use as an output buffer.
0: Use as an input buffer (initial power-on).
7.6. Port mode register (PMOD)
Bit1
PACR.1
PBCR.1
Bit0
PACR.0
PBCR.0
Address
Bit3
$13 PPULL
Bit2
PAM2
Bit1
PAM1
Bit0
HLM
Function
Bit1, 2:Select PA.1, PA.2 as I/O port or PSG output
Bit0:Hevey load mode
Bit3:Port pull-up control
R/W
PAM1, PAM2:
HLM:
PPULL:
Please see the PSG
Enable heavy load mode 0: Disable
Port pull-up MOS
0: Disable pull-up MOS
1: Enable
1: Enable pull-up MOS
7.7. Heavy load mode (HLM)
The MCU has a heavy load protection circuit for when the battery load becomes heavy, such as, when an external buzzer
sounds or an external speaker is turned on. In this mode, the crystal oscillator circuit has been backup for high gain. When setup
this mode, more power would be provided to an oscillator circuit. Unless it is nessary, be careful not to set this mode with the
software since the mode enter would delay for one instruction. Please activate heavy load driving only after setting HLM at least
one instruction wait cycle through the software. The following shows the programming setting.
HLM: 0 = Heavy load protection mode is released
1 = Heavy load protection mode is set.
HLM
0
1
HEAVYLOAD
ON
OFF
1 Instruction Cycle Time
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SH6614.PDF ] | |
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