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PDF SH6613B Data sheet ( Hoja de datos )
| Número de pieza | SH6613B | |
| Descripción | 4K 4-Bit Microcontroller | |
| Fabricantes | Sino Wealth | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de SH6613B (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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SH6613
SH6613B
SH6613C
4K 4-Bit Microcontroller with LCD Driver
Features
SH6610C-based single-chip 4-bit micro-controller
ROM: 4096×16 bits
RAM: 512×4 bits
Operation voltage: 2.4V – 6.0V
8 CMOS bi-directional I/O pins
4-Level subroutine nesting (include interrupts)
One 8-bit auto re-load timer/counter
Warm-up timer for power-on reset
Powerful interrupt sources:
- External interrupts ( INT0 ).
- Internal interrupt (Timer0).
- Internal interrupt (Base Timer).
- Port's falling edge interrupt: PORTB ( INT1 )
8-bit Base timer
LCD driver: 136 dots(1/4 duty 1/3 bias)
LCD used as scan output
Built-in dual tone PSG with one noise generator
2 Clock source
OSC: (code option select crystal or RC type)
- Crystal oscillator 32.768K
- RC oscillator: 262K
OSCX: (system register select ceramic or RC type)
- Ceramic oscillator 455K
- RC oscillator 1.8M or 2M
Instruction cycle time:
- 122.07µs for 32.768 kHz crystal
- 15.27µs for 262 kHz RC
- 8.79µs for 455KHz ceramic
- 2.22µs for 1.8 MHz RC
- 2µs for 2.0 MHz RC
Two low power operation mode: HALT and STOP
Low power consumption
General Description
SH6613 (SH6613B, SH6613C) is a single chip microcontroller integrated with SRAM, timer and dual-tone PSG, LCD driver and
I/O port. This chip builds in a dual-oscillator to enhance the total chip performance.
Pad Diagram
SSSSSSSSSSSS
EEEEEEEEEEEE
GGGGGGGGGGGG
112222222222
890123456789
SSS
EEE
GGG
333
012
SEG17 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
SEG16 45
28 SEG33
SEG15 46
27 SEG34
SEG14 47
26 COM4
SEG13 48
25 COM3
SEG12 49
SEG11 50
SEG10 51
SEG9 52
SEG8 53
SH6613
SH6613B
SH6613C
24 COM2
23 COM1
22 OSCI
21 OSCO
GND 20
PC.0
SEG7 54
19 OSCXO
SEG6 55
18 OSCXI
SEG5 56
SEG4 57
VDD
9
17 PA.0
16 PA.1
58 1 2 3 4 5 6 7 8
10 11 12 13 14 15 PA.2
_
S S S V V V V T RPP P P P P
E E E L 1 2 3 E E C. B. B. B. B. A.
GGGC
321D
S S1 3 21 03
T
E
T
1/33 V1.2
1 page  
SH6613/B/C
4. Data memory
The general-purpose data memory is organized as 512*4 bits. Because of its static feature. The RAM can maintain its data after
CPU enters the STOP or HALT mode.
5. Oscillator circuit
5.1 Circuit Configuration
SH6613/B/C has two on-chip oscillation circuits OSC and OSCX.
OSC is a low frequency crystal (Typ. 32.768KHz) or RC (Typ.262KHz) determined by the code option. This is designed for low
frequency operation. OSCX also has two types: ceramic (Typ.455KHz) or RC (1.8M or 2MHz) to determine by software option.
It is designed for high frequency operation.
It is possible to select the high speed CPU processing by a high frequency clock and select low power operation by low
operation clock. At starting of reset initialization, OSC starts oscillation and OSCX is turned off. Immediate after reset
initialization, the OSC clock is automatically selected as the system clock input source.
Oscillator Block Diagram
OSCI
OSCO
Low Frequency
Clock Oscillator
OSCXI
OSCXO
High Frequency
Clock Oscillator
Base Timer
System clock
Source Selector
& Switching control
System clock
Generator
CPU
Clock
Timing of system Clock Switching
5/33 V1.2
5 Page 
SH6613/B/C
Mixer
CH1 OUT
CH2 OUT
TIME SLOT
TIME SLOT
VOL0
VOL1
PA.1 I/O
VOL
CONTROL
PSG
PSG
PA.2 I/O
PAM1
SELECTOR1
SELECTOR2
PAM2
PA.1
PA.2
The MIXER mixes CH1-OUT and CH2-OUT into one tone output to PA.1、 PA.2, when PAM1=1、PAM2=1. Then the tone
output is controlled by the volume control bit into 4 volume levels and in the end outputted by PSG.
PA.1 & PA.2 are controlled by PAM1 & PAM2
PAM2
PAM1
0 0 PA.1:I/O PORT
0 1 PA.1:PSG output
1 0 PA.1:I/O PORT
1 1 PA.1:PSG output
Function
PA.2:I/O PORT
PA.2:I/O PORT
PA.2: PSG output
PA.2: PSG output
SEL1
0
0
1
1
SEL0
0
1
0
1
Vol. control
NO
YES
YES
YES
VOL1
0
0
1
1
VOL0
0
1
0
1
Vol. Level
1
2
3
4
Note: Don’t enable two PSG channels together to produce one tone, or it will produce some unpredicted errors. If it is necessary
to use 2 channels together (EX. To play two channel melody), don’t let the score always be the same tones as we can do, then
the unpredicted errors will not occur or it will be ignore through user hearing.
11/33
V1.2
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SH6613B.PDF ] | |
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