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HI-3110 반도체 회로 부품 판매점

Avionics CAN Controller



Holt Integrated Circuits 로고
Holt Integrated Circuits
HI-3110 데이터시트, 핀배열, 회로
HI-3110, HI-3111, HI-3112, HI-3113
May 2016
Avionics CAN Controller
with Integrated Transceiver
GENERAL DESCRIPTION
The HI-3110 is a standalone Controller Area Network
(CAN) controller with built in transceiver. The device
provides a complete, integrated, cost-effective solution for
avionics applications implementing the CAN 2.0B
specification and can be configured to comply with both the
ARINC 825 (General Standardization of CAN Bus Protocol
for Airborne Use) and CANaerospace standards. The HI-
3110 is capable of transmitting and receiving standard
data frames, extended data frames and remote frames.
The internal transceiver allows direct connection to the
CAN bus without using external components and coupled
with the host Serial Peripheral Interface (SPI), results in
minimal board space.
The HI-3110 provides the optimum solution for
applications where minimum host (MCU) overhead is
required, filtering unwanted messages using a maskable
identifier filter and storing up to 8 messages in the receive
FIFO. A flexible interrupt scheme allows real time
servicing of the FIFO by the host, if required.
Transmissions are handled using an 8 message transmit
FIFO. A Transmit Enable pin can be used by the host to
initiate a transmission. The device also provides monitor
or listen-only mode, low power sleep mode, loopback
mode for self-test and a re-transmission disable capability
(necessary to implement TTCAN protocol).
The HI-3111 is a digital only version of the HI-3110 (no
transceiver). This version provides a “protocol only”
solution for customers who wish to use an external
transceiver and may be used in situations where the
customer requires galvanic isolation between the bus and
digital protocol logic. The HI-3112 provides an option of a
CLKOUT pin instead of a SPLIT pin, which may be used as
the main system clock or as a clock input for other devices
in the system. Finally, the HI-3113 provides all options
(both CLKOUT and SPLIT pins) in a very compact QFN-44
package.
The HI-3110 family is available in industrial and full
extended temperature ranges, with a “RoHS compliant”
lead-free option. The design has been independently
validated by C&S group, GmbH, an ISO/IEC 17025
accredited test house. A copy of the test report is available
from Holt on request.
FEATURES
· Implements CAN version 2.0B with programmable bit
rate up to 1Mbit/sec. ISO 11898-5 compliant.
· Configurable to support ARINC 825 and
CANaerospace Standards.
· Serial Peripheral Interface (SPI) (20MHz).
· Standard, Extended and Remote frames supported.
· 8 maskable identifier filters.
· Filtering on ID and first two data bytes for both
Standard and Extended Identifiers.
· Loopback mode for self-test.
· Monitor (Listen-only) and Low Power Sleep Modes
with automatic wake-up possible.
· 8-message Transmit and Receive FIFOs.
· Internal 16-bit free running counter for time tagging of
transmitted or received messages.
· Permanent dominant timeout protection.
· Short Circuit Protection of -58V to + 58V on CAN_H,
CAN_L and SPLIT pins (ISO 11898-5).
· Re-transmission disable capability.
· Transmit Enable pin.
· Industrial and Full Extended temperature ranges
supported:
Industrial: -40oC to + 85oC.
Extended: -55oC to + 125oC.
PIN CONFIGURATION (Top View)
VLOGIC 1
OSCOUT 2
OSCIN 3
GP1 4
GP2 5
TXEN 6
SPLIT 7
GND 8
CANL 9
3110PSI
3110PST
3110PSM
18 INT
17 MR
16 CS
15 SO
14 SI
13 SCK
12 STAT
11 VDD
10 CANH
18-Pin Plastic SOIC - WB Package
(DS3110 Rev. J)
HOLT INTEGRATED CIRCUITS
www.holtic.com
05/16


HI-3110 데이터시트, 핀배열, 회로
BLOCK DIAGRAM
HI-3110, HI-3111, HI-3112, HI-3113
CS
SPI BUS SCK
SI
SO
SPI DECODE/
ENCODE
REGISTERS
TXEN
GP2
GP1
STAT
INT
INTERRUPTS
AND
STATUS
ERROR
STATUS
& CONTROL
OSCIN
OSCOUT
OSCILLATOR
TIME-TAG
COUNTER
BIT
TIMING
TRANSMIT
LOGIC & FIFO
HISTORY
FIFO
RECEIVE
LOGIC & FIFO
FILTERS
VLOGIC
GND
TXD
(HI-3111 only)
TRANSCEIVER
VDD
CANH
CANL
SPLIT
(see ordering
information)
RXD
(HI-3111 only)
MR
CLKOUT
(see ordering
information)
CLOCK DIV
OUT
Figure 1. Block Diagram
PRIMARY FUNCTIONS OF HI-3110 LOGIC BLOCKS
SPI PROTOCOL BLOCK
8 message FIFO with optional filters
Handles data transfers between the host and the chip Forwards message data and optional time stamp to the host
REGISTERS BLOCK
Stores configuration data
ERROR BLOCK
Detects and records errors for protocol management
BIT TIMING BLOCK
Sets the data strobe and bit period
TRANSMIT BLOCK
Manages transmission protocol
8 message FIFO
Confirmation and time stamp of each message sent
is available in the History FIFO
RECEIVER BLOCK
Manages reception protocol
STATUS AND INTERRUPT
Provides hardware and software options for managing
communications
OSCILLATOR
Configuration chooses either the crystal oscillator or and
external clock
TRANSCEIVER
Analog interface connects directly to the CAN bus
HOLT INTEGRATED CIRCUITS
2




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HI-3110 controller

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