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NXP Semiconductors |
Data Sheet: JN5142-J01
JenNet-IP Wireless Microcontroller
Overview
The JN5142-J01 is an ultra low power, high performance wireless
microcontroller suitable for use in JenNet-IP Smart Devices. The JN5142
features an enhanced 32-bit RISC processor offering high coding efficiency
through variable width instructions, a multi-stage instruction pipeline and low
power operation with programmable clock speeds. It also includes a 2.4GHz
IEEE802.15.4 compliant transceiver, 128KB of ROM, 32KB of RAM, and a
comprehensive mix of analogue and digital peripherals. The JenNet-IP
network stack is embedded in the device ROM. The operating current is
below 18mA, allowing operation direct from a coin cell.
The peripherals support a wide range of applications. They include a 2-wire
serial interface, which operates as either master or slave, a two channel
ADC with battery and temperature sensors. A large switch matrix of up to 81
elements can be supported for remote control applications. The best in
class radio current and a 0.6µA sleep timer give excellent battery life.
Block Diagram
XTAL
22R..4a4zGdGiHHoz
Power
Management
Watchdog
Timer
Voltage Supply
Monitor
O-QPSK
Modem
IEEE802.15.4
MAC
Accelerator
RAM ROM
32KB 128KB
32-bit
RISC CPU
29-byte
OTP eFuse
128-bit AES
Encryption
Accelerator
SPI
2-Wire Serial
(Master)
Timer
UART
2-Wire Serial
(Slave)
Sleep Counter
4-Chan 8-bit
ADC
Battery and,
Temp Sensors
Benefits
• Single chip optimized for
simple applications
• Very low current solution for
long battery life – over 10 yrs
• JenNet-IP Smart Devices
• Highly featured 32-bit RISC
CPU for high performance
and low power
• System BOM is low in
component count and cost
• Flexible sensor interfacing
options
Applications
• Robust and secure low power
wireless applications using
JenNet-IP
• Smart devices, for example
Thermostats, Motion sensors
etc
• Lighting Control
• Lamps
• Wall switches
• Active RFID tags
• Energy harvesting, for example
self powered light switch
Features: Transceiver
• 2.4GHz IEEE802.15.4 compliant
• 128-bit AES security processor
• MAC accelerator with packet
formatting, CRCs, address check,
auto-acks, timers
• Integrated ultra low power sleep
oscillator – 0.6µA
• 2.0V to 3.6V battery operation
• Deep sleep current 0.12µA
(Wake-up from IO)
• 0.7µA sleep with timer (1.4uA with
RAM held)
• <$0.50 external component cost
• Rx current 16.5mA
• Tx current 14.8mA
• Receiver sensitivity -95dBm
• Transmit power 2.5dBm
Features: Microcontroller
• 32-bit RISC CPU, 1 to 32MHz
clock speed
• Low power operation
• Variable instruction width for high
coding efficiency
• Multi-stage instruction pipeline
• 128KB ROM and 32KB RAM for
bootloaded program codeJenNet-
IP stack in ROM
• Master/Slave I2C 2-wire interface
• 3xPWM and Application
timer/counter
• 2 low power pulse counters
• UART
• SPI port with 3 selects
• Supply Voltage Monitor with 8
programmable thresholds
• 2- to 4-input 8-bit ADC,
comparator
• Battery and temperature sensors
• Watchdog timer and Power-on-
Reset (with brown-out) circuit
• Up to 18 DIO
Industrial temp -40°C to +125°C
6x6mm 40-lead Punched QFN
Lead-free and RoHS compliant
© NXP Laboratories UK 2012
JN-DS-JN5142-J01-J01 1v1
1
Contents
1 Introduction
1.1 Wireless Transceiver
1.2 RISC CPU and Memory
1.3 JenNet-IP Networking Stack
1.4 Peripherals
1.5 Block Diagram
2 Pin Configurations
2.1 Pin Assignment
2.2 Pin Descriptions
2.2.1 Power Supplies
2.2.2 Reset
2.2.3 32MHz Oscillator
2.2.4 Radio
2.2.5 Analogue Peripherals
2.2.6 Digital Input/Output
3 CPU
4 Memory Organisation
4.1 ROM
4.2 RAM
4.3 OTP eFuse Memory
4.4 External Memory
4.4.1 External Memory Encryption
4.5 Peripherals
4.6 Internal Non-Volatile Memory (NVM)
4.7 Unused Memory Addresses
5 System Clocks
5.1 High Speed 32MHz System Clock
5.1.1 32MHz Crystal Oscillator
5.1.2 High-Speed RC Oscillator
5.2 32kHz System Clock
5.2.1 32kHz RC Oscillator
5.2.2 32kHz Crystal Oscillator
5.2.3 32kHz External Clock
6 Reset
6.1 Internal Power-On / Brown-out Reset (BOR)
6.2 External Reset
6.3 Software Reset
6.4 Supply Voltage Monitor (SVM)
6.5 Watchdog Timer
7 Interrupt System
7.1 System Calls
7.2 Processor Exceptions
7.2.1 Bus Error
7.2.2 Alignment
7.2.3 Illegal Instruction
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© NXP Laboratories UK 2012
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