|
|
PDF Z51F0410 Data sheet ( Hoja de datos )
| Número de pieza | Z51F0410 | |
| Descripción | 8-Bit Microcontrollers | |
| Fabricantes | Zilog | |
| Logotipo |  |
|
1. Z51F0410  Hay una vista previa y un enlace de descarga de Z51F0410 (archivo pdf) en la parte inferior de esta página. Total 70 Páginas | ||
|
No Preview Available !
Z8051 Series 8-Bit Microcontrollers
Z51F0410
Product Specification
PS029502-0212
PRELIMINARY
Copyright ©2012 Zilog®, Inc. All rights reserved.
www.zilog.com
1 page  
Z51F0410
Product Specification
2.1.3 EEPROM Data Memory .................................................................................................... 44
2.2 SFR Map.................................................................................................................................. 45
2.2.1 SFR Map Summary .......................................................................................................... 45
2.2.2 SFR Map........................................................................................................................... 46
2.2.3 Compiler Compatible SFR ................................................................................................ 49
2.3 I/O Port..................................................................................................................................... 51
2.3.1 I/O Ports............................................................................................................................ 51
2.3.2 Port Register ..................................................................................................................... 51
2.3.3 P0 Port.............................................................................................................................. 52
3. Interrupt Controller ......................................................................................................................... 56
3.1 Overview .................................................................................................................................. 56
3.2 External Interrupt...................................................................................................................... 56
3.3 Block Diagram.......................................................................................................................... 58
3.4 Interrupt Vector Table............................................................................................................... 59
3.5 Interrupt Sequence................................................................................................................... 59
3.6 Effective Timing after Controlling Interrupt bit........................................................................... 61
3.7 Multi Interrupt ........................................................................................................................... 61
3.8 Interrupt Enable Accept Timing ................................................................................................ 63
3.9 Interrupt Service Routine Address............................................................................................ 63
3.10 Saving/Restore General-Purpose Registers........................................................................... 63
3.11 Interrupt Timing ...................................................................................................................... 64
3.12 Interrupt Register Overview.................................................................................................... 64
3.12.1 Interrupt Enable Register (IE, IE1, IE2, IE3).................................................................... 64
3.12.2 Interrupt Priority Register (IP, IP1) .................................................................................. 64
3.12.3 External Interrupt Flag Register (EIFLAG) ...................................................................... 65
3.12.4 External Interrupt Edge Register (EIEDGE) .................................................................... 65
3.12.5 External Interrupt Polarity Register (EIPOLA) ................................................................. 65
3.12.6 External Interrupt Enable Register (EIENAB).................................................................. 65
3.12.7 Register Map................................................................................................................... 65
3.13 Interrupt Register Description................................................................................................. 65
3.13.1 Register description for Interrupt ..................................................................................... 65
4. Peripheral Hardware....................................................................................................................... 69
4.1 Clock Generator ....................................................................................................................... 69
4.1.1 Overview........................................................................................................................... 69
4.1.2 Block Diagram................................................................................................................... 69
4.1.3 Register Map..................................................................................................................... 70
4.1.4 Clock Generator Register description ............................................................................... 70
4.1.5 Register description for Clock Generator .......................................................................... 70
4.2 BIT ........................................................................................................................................... 72
4.2.1 Overview........................................................................................................................... 72
4.2.2 Block Diagram................................................................................................................... 72
4.2.3 Register Map..................................................................................................................... 72
4.2.4 Bit Interval Timer Register description .............................................................................. 73
4.2.5 Register description for Bit Interval Timer ......................................................................... 73
4.3 WDT......................................................................................................................................... 74
4.3.1 Overview........................................................................................................................... 74
4.3.2 Block Diagram................................................................................................................... 74
4.3.3 Register Map..................................................................................................................... 74
PS029502-0212
PRELIMINARY
2
5 Page 
Z51F0410
Product Specification
Figure 6.10 Internal Reset at the power fail situation........................................................................ 148
Figure 6.11 Configuration timing when BOD RESET........................................................................ 148
Figure 7.1 Block Diagram of On-chip Debug System ....................................................................... 150
Figure 7.2 10-bit transmission packet............................................................................................... 151
Figure 7.3 Data transfer on the twin bus........................................................................................... 152
Figure 7.4 Bit transfer on the serial bus ............................................................................................ 152
Figure 7.5 Start and stop condition................................................................................................... 152
Figure 7.6 Acknowledge on the serial bus ........................................................................................ 153
Figure 7.7 Clock synchronization during wait procedure .................................................................. 153
Figure 7.8 Connection of transmission ............................................................................................. 154
Figure 8.1 Flash Memory Map.......................................................................................................... 160
Figure 8.2 Address configuration of Flash memory .......................................................................... 160
Figure 8.3 Data EEPROM memory map........................................................................................... 161
Figure 8.4 Address configuration of data EEPROM.......................................................................... 161
Figure 8.5 The sequence of page program and erase of Flash memory .......................................... 162
Figure 8.6 The sequence of bulk erase of Flash memory ................................................................. 163
Figure 8.7 Pin diagram for parallel programming.............................................................................. 169
Figure 8.8 Parallel Byte Read Timing of Program Memory............................................................... 171
Figure 8.9 Parallel Byte Write Timing of Program Memory ............................................................... 171
Figure 8.10 ISP mode ..................................................................................................................... 172
Figure 8.11 Byte-parallel mode (10pin package only)....................................................................... 172
PS029502-0212
PRELIMINARY
8
11 Page | ||
| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet Z51F0410.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| Z51F0410 | 8-Bit Microcontrollers | Zilog |
| Z51F0410HCX | 8-Bit Microcontrollers | Zilog |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |