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Número de pieza | TW8833 | |
Descripción | TFT Display Controller | |
Fabricantes | Intersil | |
Logotipo | ||
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TW8833/TW8833S -- TFT Display
Controller
Datasheet from Intersil|Techwell.
Information may change without notice
Disclaimer
This document provides technical information for the user. Intersil Corporation reserves the right to modify the
information in this document as necessary. The customer should make sure that they have the most recent data
sheet version. Intersil Corporation holds no responsibility for any errors that may appear in this document.
Customers should take appropriate action to ensure their use of the products does not infringe upon any patents.
Intersil Corporation respects valid patent rights of third parties and does not infringe upon or assist others to
infringe upon such rights.
INTERSIL|TECHWELL
1
REV A
10/25/2010
1 page TW8833/TW8833S – TFT DISPLAY CONTROLLER
0x48E – DMA Command Buffer5 Register...................................120
0x490 – DMA Read/Write Buffer1 Register...................................120
0x491 – DMA Read/Write Buffer2 Register...................................120
0x492 – DMA Read/Write Buffer3 Register...................................121
0x493 – DMA Read/Write Buffer4 Register...................................121
0x494 – DMA Read/Write Buffer5 Register...................................121
0x495 – DMA Read/Write Buffer6 Register...................................121
0x496 – DMA Read/Write Buffer7 Register..................................121
0x497 – DMA Read/Write Buffer8 Register...................................121
0x498 – SPI Flash Status Command Register.............................121
0x499 – SPI Flash Busy Control Register......................................122
0x49A – DMA Length High Byte Register.....................................122
Copyright Notice.......................................................................... 123
Trademark Acknowledgment .................................................... 123
Disclaimer..................................................................................... 123
Life Support Policy...................................................................... 123
Revision History................................................................................123
INTERSIL|TECHWELL
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5 Page TW8833/TW8833S – TFT DISPLAY CONTROLLER
Format
NTSC-M
NTSC-Japan
(1)
PAL-B, G, N
PAL-D
PAL-H
PAL-I
PAL-M
PAL-CN
SECAM
Lines
525
525
625
625
625
625
525
625
625
Fields
60
60
50
50
50
50
60
50
50
PAL-60
NTSC (4.43)
525
525
60
60
Fsc
3.58 MHz
3.58 MHz
4.43 MHz
4.43 MHz
4.43 MHz
4.43 MHz
3.58 MHz
3.58 MHz
4.406MHz
4.250MHz
4.43 MHz
4.43 MHz
Country
U.S., many others
Japan
Many
China
Belgium
Great Britain, others
Brazil
Argentina
France, Eastern Europe, Middle East, Russia
China
Transcoding
Table 1. Video Input Formats Supported
Notes: (1). NTSC-Japan has 0 IRE setup.
Component Processing
Luminance Processing
The video decoder adjusts brightness by adding a programmable value (in register BRIGHTNESS) to the
Y signal. It adjusts the picture contrast by changing the gain (in register CONTRAST) of the Y signal.
It also provides a sharpness control function through a control register. The center frequency of the
peaking filter is selectable. A coring function is provided along with the sharpness control to reduce
enhancement to the noise.
The Hue and Saturation
When decoding NTSC signals, the decoder can adjust the hue of the chroma signal. The hue is defined
as a phase shift of the subcarrier with respect to the burst. This phase shift can be programmed through a
control register.
The color saturation can be adjusted by changing the gain of Cb and Cr signals for all NTSC, PAL and
SECAM formats. The Cb and Cr gain can be adjusted independently for flexibility.
INTERSIL|TECHWELL
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REV A
10/25/2010
11 Page |
Páginas | Total 70 Páginas | |
PDF Descargar | [ Datasheet TW8833.PDF ] |
Número de pieza | Descripción | Fabricantes |
TW8833 | TFT Display Controller | Intersil |
TW8833S | TFT Display Controller | Intersil |
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