|
|
PDF AD009-041 Data sheet ( Hoja de datos )
| Número de pieza | AD009-041 | |
| Descripción | Remote controller | |
| Fabricantes | ETC | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de AD009-041 (archivo pdf) en la parte inferior de esta página. Total 14 Páginas | ||
|
No Preview Available !
AD009-041
AD009-041 Remote controller
1. General Descriptions
The AD009-041 a high-performance 4-bit RISC micro-controller embedded up to 2KX12 bits OTP, 32X4
bits SRAM, 10 Input/Output pins, one input pin and built-in one IR LED drive pin. it’s flexible and cost-
effective solution for remote control of TV, Fans, Air conditioners ... etc.
2. Features
MCU Operating voltage: 1.8V to 3.6V
Operation frequency: MCU run 2 MIPS
Memory Size
Program ROM size: 2K X12 bits (OTP type)
SRAM size: 32x4 bits
Wake up function for power-down mode
HALT mode wake up source: RTC timer overflow or PA0~3, PB0~3 and PD0~3 edge trigger.
Provided 10 input /output pins: each I/O has bit programmable as input or output port, these 10 I/Os
also provided edge trigger wake up function and pull up resistors configured by registers.
(a) They are provided with high sink current 20mA @VDD=3V, VOL=0.5V.
(b) They are provided with drive current 7mA @VDD=3V, VOH=2.5V.
(c) Pull up 150k ohm resistor.
Provide 1 input pin (PA3) shared with VPP pin, pull up 150k ohm resistor and edge trigger wake up
function.
Built-in one IR LED drive pin.
( Sink current : IOL=210mA at VDD=3V and VOL=0.3V )
One 8 bits timer, clock source of timer is FMCK /8192( or 4096,2048,1024 ), the content of timer can be
cleared and read by program.
Built-in internal RC OSC 8 MHz ----
frequency deviation within ±2%, VDD=1.8V~3.6V, temp= -20 ºC ~70 ºC
Support 1.5 cycle length instruction (NOP15) to generate IR waveform by software.
Four reset condition
Low voltage reset (LVR=1.5V)
Power on RC-reset
Watch dog timer overflow reset ( WDT period is 0.26 Sec )
Page 1 of 14
Version 1.0
1 page  
AD009-041
To read OTP ROM valid data, use DMA2~DMA0 registers as address pointer. After these registers
(DMA0~2) are specified by software, the 12bits data of ROM can be moved to A register by three
instructions, they are “LD A, (DMDL)”, “LD A, (DMDM)” and “LD A, (DMDH)”. The three instructions
mentioned above are two cycle instruction, all others instructions are single cycle instruction.
Symbol
DMA0
DMA1
DMA2
DMDL
DMDM
DMDH
Addr
18H
19H
1AH
1CH
1DH
1EH
R/W
R/W
R/W
R/W
R
R/W
R
Reset D3 D2 D1 D0 Description
xxxx DMA0.3 DMA0.2 DMA0.1 DMA0.0 DMA0~DMA2 three registers built a 11 bit
xxxx DMA1.3 DMA1.2 DMA1.1 DMA1.0 addressing space (DMA2.3 not including)
xxxx DMA2.3 DMA2.2 DMA2.1 DMA2.0 for read PROM data, DMA0 is lowest
nibble address, DMA2 is highest nibble
address.
DMA2.3: It’s a register only, but for PROM
address setting is useless.
xxxx DMDL.3 DMDL.2 DMDL.1 DMDL.0 DMDL is used to read low nibble data of
PROM by address DMA0~ DMA2.
xxxx DMDM.3 DMDM.2 DMDM.1 DMDM.0 DMDM is used to read middle nibble data
of PROM by address DMA0 ~ DMA2.
Writing this register with data 05h will
clear watch dog timer (WDT)
xxxx DMDH.3 DMDH.2 DMDH.1 DMDH.0 DMDH is used to read the high nibble data
PROM by address DMA0~DMA2
For example, assume the data of address 156H is 587H.
LD A, #1
LD (DMA2), A
LD A, #5
LD (DMA1), A
LD A, #6
LD (DMA0), A ; ROM address = 156H
LD A, (DMDL) ; A register = 7H ; low nibble data of ROM address 156H
LD A, (DMDM) ; A register = 8H; middle nibble data of ROM address 156H
LD A, (DMDH) ; A register = 5H; high nibble data of ROM address 156H
5.2 SRAM and I/O Memory Map
AD009-041 series provided 32 nibbles SRAM on the locations $20H~$3FH, these address of SRAM is
different from PROM’s address.
Direct Addressing (use MAH ) Real SRAM Address
SRAM MAP
MAH=XH
00H~1FH
( MAH no effect )
MAH=0H
20H~3FH
00H~1FH
Common I/O port and SFR(special function
register) register
USER SRAM (32x4)
5.2.1 I/O Memory Map
The I/O memory map consists of common I/O and extended I/O. These I/O provide some data operation
instructions as the following:
5.2.2 Common I/O
The previously described common block is defined as the common I/O block. A common I/O provided
LD/ADC/SBC/OR/AND/XOR/INC/DEC/RLC/RRC/CMP/ADR operation. SET, CLR ( bit set/clear ) can only be
operated on the address range from 00H to 0FH.
Page 5 of 14
Version 1.0
5 Page 
AD009-041
DATA_PD 0DH R/W xxxx X
DPD2 DPD1 DPD0 Read Port D data from PD0~PD2 port and
write to PD0~PD2 ( I/O direction is define
by IOC_PD register)
Extended I/O
PDPU
04H W 0000 X
PDPU.2 PDPU.1 PDPU.0 Port D pull up 150K ohm resistor
0: Port D pull up resistor disabled
1: Port D pull up resistor enabled
PDWK
08H W 0000 X
PDWK.2 PDWK.1 PDWK.0 Port D wake up enable control
0: Port D wake up disabled
1: Port D wake up enabled
Whether all 3 bits of the Port D is input or output port depends on IOC_PD control register.
Port D also provided edge trigger (rising or falling) wake up and pull up resistor 150K, function just like Port
A or Port B.
6. Wake up function for keyboard scan in halt mode
All Port A, Port B, Port D are provided a special wake up function for hardware keyboard scan in halt mode
automatically.This function can be enabled by option, and individual PIN can be enabled or disabled by
corresponding wake up registers.
It’s built-in one low power RC oscillator 13KHz ± 50% for keyboard scan function operation.
The detail sequence of keyboard scan is described below:
1. Keyboard scan function enabled by KBSCEN option.
2. Set all scan key I/O to input mode.
3. Pull up resistor enabled by PAPU, PBPU or PDPU register.
4. Wake up function enabled by PAWK, PBWK or PDWK register. Keyboard scan function can be
disabled for individual pin by corresponding wake up control registers set to 0.
5. Execute HALT instruction into power down mode.
6. When in halt mode, at the same time only one I/O port direction switch to output state and others are in
input state with pull up resistor. The output port will output one low-pulse from PA2~PA0, PB3~PB0 and
PD2~PD0 sequentially if all wake up registers of all I/O port are enabled. The period of keyboard scan time
is fixed as shown below:
7. In halt mode, MCU will be waked up by rising or falling edge of I/O ports which key scan function is
enabled.
Ta=1.2ms±50%, Tb=28ms±50%
PA2
PA1
PA0
PB3
PB2
PB1
PB0
PD2
PD1
PD0
PA3(Input)
Pull high
Ta
Ta
Tb
PA2 output low
PA2 input with
pull up resistor
PA1 output low
PA1 input with pull
up resistor
The waveform of keyboard scan function
Page 11 of 14
Version 1.0
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet AD009-041.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| AD009-041 | Remote controller | ETC |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |