|
|
PDF PS10 Data sheet ( Hoja de datos )
| Número de pieza | PS10 | |
| Descripción | Quad Power Sequencing Controller | |
| Fabricantes | Supertex | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de PS10 (archivo pdf) en la parte inferior de esta página. Total 9 Páginas | ||
|
No Preview Available !
PS10
Quad
Power Sequencing Controller
Features
► Sequencing of four supplies, ICs, or subsystems
► Independently programmable delays between open
drain PWRGD flags (5.0 to 200ms)
► ±10 to ±90V operation
► Tracking in combination with Schottky diodes
► Input supervisors including:
• UV/OV lock out/enable
• Power-on-Reset (POR)
► Low power consumption, 0.4mA supply current
► Available in a space saving 14-Lead SOIC package
Applications
► Power supply sequencing
► -48V telecom and networking distributed systems
► -24V cellular and fixed wireless systems
► -24V PBX systems
► +48V storage systems
► FPGA, microprocessor tracking
► Industrial/embedded system timing/sequencing
► High voltage MEMs driver’s supply sequencing
► High voltage display driver’s supply sequencing
General Description
Many of today’s high performance FPGA’s, microprocessors,
DSP and industrial/embedded subsystems require sequencing
of the input power. Historically this has been accomplished
by: i) discretely using comparators, references & RC circuits;
ii) using expensive programmable controllers; or iii) with low
voltage sequencers requiring resistor drop downs and several
high voltage optocoupler or level shift components.
The PS10 saves board space, improves accuracy, eliminates
optocouplers or level shifts and reduces overall component
count by combining four timers, programmable input UV/
OV supervisors, a programmable POR, and four 90V open
drain outputs. A high reliability, high voltage, junction isolated
process allows the PS10 to be connected directly across the
high voltage input rails.
The power-on-reset interval (POR) may be programmed by a
capacitor on CRAMP. To sequence additional systems, multiple
PS10s may be daisy-chained together. If at any time the input
supply falls outside the UV/OV detector range, the PWRGD
outputs will immediately become IN-ACTIVE.
The PS10 is available in a space saving 14-Lead SOIC
package.
Typical Application Circuit
GND or +48V
487KΩ
6
UV
14
VIN
6.81KΩ
9.76KΩ
5
OV
7
VEE
TB
11
PS10
TC TD
12 13
RAMP
10
PWRGD-D 1
PWRGD-C 2
PWRGD-B 3
PWRGD-A 4
RTB RTC RTD
10nF
-48V or GND
Notes:
1. Under Voltage Shutdown (UV) set to 37V.
2. Over Voltage Shutdown (OV) to 57.8V.
/EN
DC/DC
CONVERTER
+12V
COM
/EN
DC/DC
CONVERTER
+5V
COM
/EN
DC/DC
CONVERTER
+3.3V
COM
/EN
DC/DC
CONVERTER
+2.5V
COM
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
1 page  
PS10
Then:
(VEEUV(on)) = 1.22 x (R1+R2+R3)/(R2+R3)
(VEEUV(on)) = 1.22 x (487k+6.65k+9.31k)/(6.65k+9.31k)
= 38.45V
And:
PWRGD Flags Delay Programming
When the ramp voltage hits VINT - 1.17V, PWRGD-A be-
comes active indicating that the input supply voltage is within
the programmed limits. PWRGD-B goes active after a pro-
grammed time delay after PWRGD-A went active. PWRGD-
C goes active after a programmed time delay after PWRGD-
B went active. PWRGD-D goes active after a programmed
time delay after PWRGD-C went active.
(VEEOV(on)) = 1.12 x (R1+R2+R3)/R3
(VEEOV(on)) = 1.12 x (487kΩ +6.65kΩ +9.31kΩ)/9.31kΩ
= 60.51V
Therefore, the circuit will start when the input supply voltage
is in the range of 38.45V to 60.51V.
Undervoltage/Overvoltage Protection
The resistors connected from TB, TC, and TD to VEE pin
determines the delay times between the PWRGD flags.
The value of the resistors determines the capacitor charging
and discharging current of a triangular wave oscillator. The
oscillator output is fed into an 8-bit counter to generate the
desired time delay.
The respective time delay is defined by the following equa-
tion:
GND
UVOFF
UVON
VIN
OVON
OVOFF
tTX = (255 x 2 x COSC x VPP)/ICD
and
ICD = VBG / (4 x RTX)
Where:
PWRGD SET RESET
tPWRGD-A is the time delay from VEEUV(on) to PWRGD-A going
active. It can be approximated by:
tPWRGD-A = CRAMP x (VINT-1.17)/IRAMP
where:
CRAMP = capacitor connected from RAMP pin to VEE pin
VINT = internal regulated power supply voltage (10V typ.)
IRAMP = 10µA charge current
tTX = Time delay between respective PWRGD flags
COSC = 120pF (internal oscillator capacitor)
VPP = 8.2V (peak-to-peak voltage swing of oscillator)
ICD = Charge and discharge current of oscillator
VBG = 1.17V (internal band gap reference)
RTX = Programming resistor at TB, TC, or TD
Combining the two equations and solving for RTX yields:
RTX = (VBG x tTX) / (2040 x COSC x VPP)
= 0.585 x 106 x tTX
For a time delay of 200ms
RTX = 0.585 x 106 x 0.2 = 117kΩ
For a time delay of 5ms
RTX = 0.585 x 106 x 0.005 = 2.925kΩ
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
5
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet PS10.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| PS10 | Quad Power Sequencing Controller | Supertex |
| PS10 | Diode ( Rectifier ) |  American Microsemiconductor |
| PS1000FL | FAST RECOVERY RECTIFIERS |  Compact Technology |
| PS1001 | PHOTO COUPLER INDUSTRIAL USE |  NEC |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |