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PDF WT61P6 Data sheet ( Hoja de datos )
| Número de pieza | WT61P6 | |
| Descripción | Embedded Micro-Controller | |
| Fabricantes | Weltrend | |
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Weltrend Semiconductor, Inc.
WT61P6
Embedded Micro-Controller for Monitor
(Flash Memory Type)
Data Sheet
REV. 1.01
Oct 26, 2004
The information in this document is subject to change without notice.
Weltrend Semiconductor, Inc. All Rights Reserved.
2F, No. 24, Industry E. 9th RD., Science-Based Industrial Park, Hsin-Chu, Taiwan
TEL:886-3-5780241 FAX:886-3-5794278.5770419
Email:[email protected]
1 page  
WT61P6 v1.01
Monitor Controller
FUNCTIONAL DESCRIPTION
CPU
8-bit 8051 compatible CPU with 16-bit address bus and 8-bit data bus operates at 12/24MHz.
RAM
The 1536 bytes SRAM include:
128 bytes internal SRAM are from $0000H to $007FH (direct & indirect addressing)
128 bytes internal SRAM are from $0080H to $00FFH (indirect addressing)
768 bytes external SRAM are from $0080H to $037FH
256 bytes external SRAM are from $0400H to $04FFH for 1st DDC EDID
256 bytes external SRAM are from $0500H to $05FFH for 2nd DDC EDID
Flash Memory
128K bytes flash memory for program. Address is located from $00000h to $1FFFFh.
8031 (P3.5,P3.4) ports switch the flash memory bank.
When 8031 address[15]=0, (P3.5,P3.4)=(x,x) => flash address[16:0]=00000h-07FFFh.
When 8031 address [15]=1, (P3.5,P3.4)=(0,0) => flash address[16:0]=08000h-0FFFFh.
When 8031 address [15]=1, (P3.5,P3.4)=(0,1) => flash address[16:0]=10000h-17FFFh.
When 8031 address [15]=1, (P3.5,P3.4)=(1,0) => flash address[16:0]=18000h-1FFFFh.
Weltrend Semiconductor, Inc.
Page 5
5 Page 
WT61P6 v1.01
Monitor Controller
I/O Port D
The PD0~PD7 are the general purpose IO shared with some special functions. When the special
function is disabled, it is a general purpose I/O port. If it is configured as output, it could source/sink
6mA. If it is configured as input and PdnHE is “0”, it has an internal pull-up resistor. If the PDn is
configured as input and the PDnHE is “1”, it doesn’t have an internal pull-up resistor.
INTERNAL_DATA_BUS
DATA[0]
D Q PD0HE
WRITE_PD_CTRL2
RESET
C QN
R
DATA[0]
D Q PD0OE
WRITE_PD_CTRL
RESET
C QN
R
DATA[0]
D Q PD0O
PD0
WRITE_PD_DATA C QN
R
RESET
READ_PD_DATA
DATA[0]
Fig.4 Structure of PD0
Port D control and data register
Name Addr R/W Initial Bit 7
PD_CTRL 0006h W 00h PD7OE
PD_DATA 0007h
R
W
ffh
ffh
PD7
PD7
PD_CTRL2 000Ah W 00h PD7HE
Bit 6
PD6OE
PD6
PD6
PD6HE
Bit 5
PD5OE
PD5
PD5
PD5HE
Bit4
PD4OE
PD4
PD4
PD4HE
Bit 3
PD3OE
PD3
PD3
PD3HE
Bit 2
PD2OE
PD2
PD2
PD2HE
Bit 1
PD1OE
PD1
PD1
PD1HE
Bit 0
PD0OE
PD0
PD0
PD0HE
Bit Name
Description
Port Dn Output Enable.
PDnOE When it is “1”, PDn is configured as an output pin.
When it is “0”, PDn is configured as an input pin with internal pull-up resistor.
This bit controls the output level when the corresponding PDnOE bit is set.
PDn (W) When PDn=1, PDn pin outputs high level.
When PDn=0, PDn pin outputs low level.
PDn (R)
When PDnOE=1 (i.e. output port), the data of this bit is same as PDn (W).
When PDnOE=0, this bit indicates the input level. “1” is high and “0” is low.
Configured the Port Dn pull-up resistor.
PDnHE When PDnHE =1, PDn pin without pull-up resistor.
When PDnHE =0, PDn pin with pull-up resistor.
Weltrend Semiconductor, Inc.
Page 11
11 Page | ||
| Páginas | Total 53 Páginas | |
| PDF Descargar | [ Datasheet WT61P6.PDF ] | |
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