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PDF UP6205 Data sheet ( Hoja de datos )
| Número de pieza | UP6205 | |
| Descripción | Compact Dual-Phase Synchronous-Rectified Buck Controller | |
| Fabricantes | uPI Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de UP6205 (archivo pdf) en la parte inferior de esta página. Total 17 Páginas | ||
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Preliminary
uP6205
Compact Dual-Phase
Synchronous-Rectified Buck Controller
General Description
The uP6205 is a compact dual-phase synchronous-rectified
Buck controller specifically designed to deliver high quality
output voltage for high power applications. This part is
capable of delivering up to 60A output current owing to its
embedded bootstrapped drivers that support 12V + 12V
driving capability. The uP6205 features configurable gate
driving voltage for maximum efficiency and optimal
performance. The built-in bootstrap diode simplifies the
circuit design and reduces external part count and PCB
space.
The output voltage is precisely regulated to internal 0.6V
or external reference voltage from 0.4V to 2.5V. The uP6205
adopts lossless R
current sensing technique for
DS(ON)
channel current balance and over current protection.
A MODE pin programs single- or dual- phase operation
making the uP6205 ideally suitable for dual power input
applications such as PCIE interfaced graphic cards. When
programmed as automatic mode, the uP6205 operates in
single phase at light load condition and maintains high
efficiency over a wide range of the output current.
This part features comprehensive protection functions
including over current protection, input/output under voltage
protection, over voltage protection and over temperature
protection.
Other features include adjustable soft start, adjustable
operation phase, and quick response to step load transient.
With aforementioned functions, this part provides
customers a compact, high efficiency, well-protected and
cost-effective solutions. This part is available in spacing-
saving VQFN4x4-24L or VQFN3x3-16L package.
Features
Operate with 4.5V ~13.2V Supply Voltage
Support Single- and Two- Phase Operation
±2.0% Over Line Voltage and Temperature
Simple Single-Loop Voltage-Mode Control
12V Bootstrapped Drivers with Internal
Bootstrap Diode
Lossless RDS(ON) Current Sensing
Adjustable Operation Frequency form 50kHz to
1MHz Per Phase
External Compensation
Adjustable Over Current Protection
Adjustable Soft Start
VQFN4x4 - 24L or VQFN3x3 - 16L Package
RoHS Compliant and 100% Lead (Pb)-Free
Applications
Middle-High End GPU Core Power
High End Desktop PC Memory Core Power
Low Output Voltage, High Power Density DC-DC
Converters
Voltage Regulator Modules
Ordering Information
Order Number Package Type
Remark
uP6205AQAG VQFN4x4 - 24L
uP6205BQAD VQFN3x3 - 16L Without REFIN Pin
uP6205CQAD VQFN3x3 - 16L Without MODE Pin
Note: uPI products are compatible with the current IPC/
JEDEC J-STD-020 and RoHS requirements. They are 100%
matte tin (Sn) plating and suitable for use in SnPb or Pb-
free soldering processes.
uPI Semiconductor Corp., http://www.upi-semi.com
Rev. P01, File Name: uP6205-DS-P0103
1
1 page  
Preliminary
uP6205
Functional Description
The uP6205 is a compact dual-phase synchronous-rectified
Buck controller specifically designed to deliver high quality
output voltage for high power applications. This part is
capable of delivering up to 60A output current owing to its
embedded bootstrapped drivers that support 12V + 12V
driving capability. The built-in bootstrap diode simplifies the
circuit design and reduces external part count and PCB
space.
The output voltage is precisely regulated to internal 0.6V
reference voltage or external reference voltage from 0.4V
to 2.5V. The uP6205 adopts RDS(ON) current sensing
technique for channel current balance, and over current
protection.
This part features comprehensive protection functions
including over current protection, input/output under voltage
protection, over voltage protection and over temperature
protection.
Other features include internal soft start, adjustable
operation phase number and quick response to step load
transient. With aforementioned functions, this part provides
customers a compact, high efficiency, well-protected and
cost-effective solutions. This part is available in VQFN4x4
- 24L or VQFN3x3 - 16L packages.
Internal 9V and 5V LDO Regulators
The uP6205 integrates 9V and 5V LDO regulators for gate
drivers and internal control circuitry respectively as shown
in Figure 1.
The 9V LDO receives input voltage at VCC12 pin and outputs
a regulated voltage at PVCC9 pin for the lower gate drivers
and the bootstrap circuit for the upper gate drivers, providing
flexible gate driving voltage for maximum efficiency and
optimal performance. When driving with 9V gate voltage,
the converter reduces 25% power dissipation in the drivers
and maintains high efficiency comparing to 12V driving
voltage. This enables the uP6205 to drive MOSFETs with
large input capacitors and provides up to 60A output current
without overheating the controller itself.
When the VCC12 pin is left open, the VCC9 and PVCC9
pins could receive well decoupled 4.5V~13.2V voltage for
gate drivers as shown in Figure 2. Since the uP6205 adopts
R current sensing technique for current balance and
DS(ON)
over current protection, always consider the RDS(ON) with
the lowest possible gate driving voltage. If the gate driving
voltage is expected to be lower than 7V, special
consideration should be paid to the threshold voltage of
the MOSFETs.
Bootstrap diodes are embedded to facilitate PCB design
and reduce the total BOM cost. No external Schottky diode
is required. However, if the VCC9 and PVCC9 pins voltage
are expected to be lower than 5V, external Schottky diode
is highly recommended to get highest gate driving voltage
for high side MOSFET.
VIN = 10.8~13.2V
VCC12
PVCC9
VCC9
9V
LDO
uP6205
Gate
Drivers
5V
LDO
Control
Circuirty
Figure 1. 9V Drive Application
VIN = 4.5~13.2V
VCC12
PVCC9
9V
LDO
uP6205
Gate
Drivers
VCC9
5V
LDO
Control
Circuirty
Figure 2. Bypass the Internal 9V LDO Regulator.
The VCC pin should be locally bypassed by a minimum
1uF ceramic. Place the capacitor physically near the VCC
pin.
An internal linear regulator regulates VCC input to a 5VCC
voltage for internal control logic circuit as shown in Figure
1 and 2. No external bypass capacitor is required for the
5VCC voltage.
Power On Reset and Initialization
The uP6205 continuously monitors VCC9 pin voltage for
power on reset (POR) to ensure the supply voltage is high
enough for normal operation of the device. The POR
threshold level is typically 4.3V at VCC9 rising.
Reference Voltage Selection
The uP6205 features selectable internal or external
reference voltage. The REFIN voltage level is checked at
POR to select the desired reference voltage. Internal 0.6V
reference voltage is selected if VREFIN > 3.3V at POR,
otherwise external reference voltage would be selected.
uPI Semiconductor Corp., http://www.upi-semi.com
Rev. P01, File Name: uP6205-DS-P0103
5
5 Page 
Preliminary
uP6205
Parameter
Soft Start
Soft Start Current
Re-Soft Start Threshold Level
Protection
Over Temperature Protection
Over Temperature Hysteresis
Symbol
Test Conditions
Electrical Characteristics
Min Typ Max Units
ISS VSS = 0V
VSS_HICCUP
7 10 13 uA
-- 0.5 -- V
150 OC
20 OC
Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device.
These are for stress ratings. Functional operation of the device at these or any other conditions beyond those
indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may remain possibility to affect device reliability.
Note 2. Devices are ESD sensitive. Handling precaution recommended.
Note 3. θJA is measured in the natural convection at TA = 25°C on a low effective thermal conductivity test board of
JEDEC 51-3 thermal measurement standard.
Note 4. The device is not guaranteed to function outside its operating conditions.
uPI Semiconductor Corp., http://www.upi-semi.com
Rev. P01, File Name: uP6205-DS-P0103
11
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet UP6205.PDF ] | |
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