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PDF SH6511 Data sheet ( Hoja de datos )
| Número de pieza | SH6511 | |
| Descripción | 16K 4-Bit Microcontroller | |
| Fabricantes | Sino Wealth | |
| Logotipo |  |
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SH6511/SH6511B
16K 4-Bit Microcontroller with LCD Driver
Features
SH6610-based s ingle-chip 4-bi t M icrocontroller with
LCD driver
ROM: 16 K × 16 bits (bank switched)
RAM: 512 × 4 bit s (system co ntrol register & data
memory)
Operating Voltage Range: 2.4V - 5.5V
8 CMOS I/O ports
4 level subroutine nesting including interrupts`
One 8-bit timer with pre-divider circuit
Warm-up timer for power-on reset
Pow erful interrupt sources:
-Timer0 interrupt
-Port B interrupt (falling edge)
System clock: 2 M Hz single-p in v oltage-controlled
oscillator
Table Bran ch a nd Return C onstant I nstructions for
Table Data Generation
Data pointer with special system register control
Two low power operating modes - HALT and STOP
Instruction cycle tim e: 2 µs for 2 M Hz v oltage-
controlled oscillator
Built-in 2-channel PSG for sound effects, switch able to
noise channel
D irectly drives speaker
Type B LCD drive circuit
LCD driver: 40 × 8 (1/8 duty cycle, 1/4 bias)
LCD off by programming LCDOFF register
Available in CHIP FORM
General Description
SH6511/SH6511B is a single chip 4 b it µC dedicated chip for handheld games. This device integrates a SH6610 4-bit CPU
core with RAM, ROM, timer, 2-channel PSG, and dot matrix LCD driver.
Pad Configuration
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SS
EE
GG
21
09
1 23
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48 47 46
S S S S S SS S S
E E E E E EE E E S S
G G G G G GS GG E E
1 1 1 1 1 11 1 1 G G
8 7 6 5 4 32 1 0 9 8
4 5 6 7 8 9 10 11 12 13 14 15
16
17
18
19
20
SH6511/
SH6511B
21
22
23
24
25
26
27
GV
ND
DD
42 39
28
29
30
31
45 44 43 41 40 38 37 36 35 34 33 32
SS
EE
GG
34
90
T
E
S
T
R
E
S
E
A
O
U
T
O OO
P SP
0 C1
I
PP
AA
01
PP
AA
23
T
P
B
0
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
PB3
PB2
PB1
1/22
Ver 2.2
http://www.Datasheet4U.com
1 page  
(c) System Registers (continued)
Bit 3
Bit 2
Bit 1
$10 DPL.3 DPL.2 DPL.1
$11 - DPM.2 DPM.1
$12 - DPH.2 DPH.1
$13 C1.3 C1.2 C1.1
$14 C1M C1.6 C1.5
$15 C2.3 C2.2 C2.1
$16 C2.7 C2.6 C2.5
$17
C2.11 C2.10.
C2.9
$18
C2M
C2.14 C2.13
$19
VOL1
VOL0 CH2EN
Bit 0
DPL.0
DPM.0
DPH.0
C1.0
C1.4
C2.0
C2.4
C2.8
C2.12
CH1EN
$1A -
-
P1.1
P1.0
$1B -
-
P2.1
P2.0
$1C
-
TM.2
TM.1 LCDOFF
$1D - - - -
$1E - - - -
$1F - BNK2 BNK1 BNK0
SH6511/SH6511B
R/W
R/W
R/W
R/W
W
W
W
W
W
W
W
W
W
W
-
-
W
Remarks
Data Pointer for INX low nibble
Data Pointer for INX middle nibble
Data Pointer for INX high nibble
PSG Channel 1 low digit
PSG Channel 1 high digit
PSG Channel 2 low digit
PSG Channel 2
PSG Channel 2
PSG Channel 2 high digit
Bit 0: PSG Channel 1 enable
Bit 1: PSG Channel 2 enable
Bit 2, Bit 3: Volume Control (Initially 0, no sound)
PSG 1 Prescaler
PSG 2 Prescaler
Bit 0: LCD Power Control
Bit 2, Bit 1: Reserved for TEST Mode (TMR)
Reserved for ICE
Reserved for ICE
Bank Register for ROM (BNK), bit 3 reserved for ICE
(d) Data Pointer
Data m emory can be i ndirectly addr essed by the D ata
Pointer. Pointer addre ss is lo cated in reg ister D PM
(3-bits) and DPL (4-bits). The addressing range can have
128 locations. Pseudo index address (INX) is used to read
or write Data memory, then RAM address bit9-bit0 comes
from DPH, DPM and DPL.
3. ROM
SH6511/SH6511B can addr ess up to 16K × 16 b its of
program area from $000 to $3FFF.
ROM SPACE in the system is 16384 × 16 bits.
(a) Vector Address Area ($000 to $004)
The progra m i s s equentially executed. An area from
address $000 through $004 is reserved for special interrupt
service routines as starting execution of a vector address.
Address
Instruction
Remarks
$000
$001
$002
$003
$004
JMP
-
JMP
-R
JMP
Jump to RESET
Reserved
Jump to TIMER0
eserved
Jump to PB
(Port B)
* JMP can be replaced by any other instruction.
(b) Table Data Reference
Table Data can be stored in program memory and can be
referenced by us ing Table Bran ch (TJMP) and R eturn
Constant (RTNW) instructions. The Table Branch Register
(TBR) and Accumulator (A) is placed by an offset address
in program R OM. TJMP instruc tion branch int o ad dress
((PC11 - PC8) ×( 28 ) + (TBR, A)). The addre ss is
determined by RTNW to return look-up value into (TBR, A).
ROM code bit7-bit4 is placed into TBR and bit3-bit0 into A.
5/22 Ver 2.2
5 Page 
SH6511/SH6511B
7. LCD
The LC D has 8 c ommon sig nal pad s, a controller, a LCD v oltage generator, an d 40 segment dr iver pads. T he con troller
consists of display data RAM and a duty generator. LCD is 1/8 duty, and 1/4 bias. The LCD data RAM is a dual port RAM that
automatically transfers data to segment. The LCD can be turned off with the internal LCDOFF register.
(a) LCD RAM Area Configuration:
Address
Bit3
Bit2
Bit1
Bit0
$300
SEG1
SEG1
SEG1
SEG1
$301
SEG2
SEG2
SEG2
SEG2
$302
SEG3
SEG3
SEG3
SEG3
$303
SEG4
SEG4
SEG4
SEG4
$304
SEG5
SEG5
SEG5
SEG5
$305
SEG6
SEG6
SEG6
SEG6
$306
SEG7
SEG7
SEG7
SEG7
$307
SEG8
SEG8
SEG8
SEG8
$308
SEG9
SEG9
SEG9
SEG9
$309
SEG10
SEG10
SEG10
SEG10
$30A
SEG11
SEG11
SEG11
SEG11
$30B
SEG12
SEG12
SEG12
SEG12
$30C
SEG13
SEG13
SEG13
SEG13
$30D
SEG14
SEG14
SEG14
SEG14
$30E
SEG15
SEG15
SEG15
SEG15
$30F
SEG16
SEG16
SEG16
SEG16
$310
SEG17
SEG17
SEG17
SEG17
$311
SEG18
SEG18
SEG18
SEG18
$312
SEG19
SEG19
SEG19
SEG19
$313
SEG20
SEG20
SEG20
SEG20
$314
SEG21
SEG21
SEG21
SEG21
$315
SEG22
SEG22
SEG22
SEG22
$316
SEG23
SEG23
SEG23
SEG23
$317
SEG24
SEG24
SEG24
SEG24
$318
SEG25
SEG25
SEG25
SEG25
$319
SEG26
SEG26
SEG26
SEG26
$31A
SEG27
SEG27
SEG27
SEG27
$31B
SEG28
SEG28
SEG28
SEG28
$31C
SEG29
SEG29
SEG29
SEG29
$31D
SEG30
SEG30
SEG30
SEG30
$31E
SEG31
SEG31
SEG31
SEG31
$31F
SEG32
SEG32
SEG32
SEG32
$320
SEG33
SEG33
SEG33
SEG33
$321
SEG34
SEG34
SEG34
SEG34
$322
SEG35
SEG35
SEG35
SEG35
$323
SEG36
SEG36
SEG36
SEG36
$324
SEG37
SEG37
SEG37
SEG37
$325
SEG38
SEG38
SEG38
SEG38
$326
SEG39
SEG39
SEG39
SEG39
$327
SEG40
SEG40
SEG40
SEG40
Duty
COM4
COM3
COM2
COM1
11/22
Ver 2.2
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet SH6511.PDF ] | |
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