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PDF MTV412M Data sheet ( Hoja de datos )
| Número de pieza | MTV412M | |
| Descripción | 8051 Embedded Monitor Controller | |
| Fabricantes | Myson | |
| Logotipo |  |
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MYSON-CENTURY
TECHNOLOGY
MTV412M
(Rev 0.9)
8051 Embedded Monitor Controller
128K Flash Type with ISP
FEATURES
• 8051 core, 12MHz operating frequency with double CPU clock option
• 0.35um process; 3.3V/5V power supply; 5V I/O tolerant
• 1024-byte RAM; 128K-byte program Flash-ROM support In System Programming (ISP) without boot code
• Maximum 14 channels of PWM DAC
• Maximum 38 (44-pin) or 36 (42-pin) I/O pins
• SYNC processor for composite separation/insertion, H/V polarity/frequency check and polarity adjustment
• Clock output to drive other devices
• Built-in low power reset circuit
• Compliant with VESA DDC1/2B/2Bi/2B+ standard
• Triple slave IIC addresses; two H/W auto transfer DDC1/DDC2x data for both D-sub and DVI interfaces
• Single master IIC interface for internal device communication
• Maximum 4-channel 8-bit A/D converter
• Flash-ROM program code protection selection
• 42-pin SDIP or 44-pin PLCC/PQFP package
GENERAL DESCRIPTIONS
The MTV412M micro-controller is an 8051 CPU core embedded device targeted for LCD Monitor, LCD TV or
smart pa nel app lications. It includes an 8 051 C PU c ore, 10 24-byte SR AM, on -chip 1 6K-bit EEPROM, 1 4
PWM DACs, VESA DDC for both D-sub and DVI interfaces, 4-channel 8-bit ADC, hardware ISP without boot
code and a 128K-byte internal program Flash-ROM in 42-pin SDIP, 44-pin PLCC/PQFP package.
P1.0-7
P3.0-2
P3.4
RST
X1
X2
CKO
8051
CORE
P0.0-7
P2.0-3
RD
WR
ALE
INT1
P7.0-7
P6.0-7
P5.0-6
P4.0-2
AUX
I/O
P0.0-7
P2.0-3
RD
WR
ALE
INT1
XFR
ADC
AD0-3
PWM DAC
DA0-13
16K-BIT
EEPROM
AUXRAM &
DDCRAM1 &
DDCRAM2
H/VSYNC
CONTROL
HSYNC
VSYNC
HBLANK
VBLANK
HCLAMP
VCOAST
DDC & IIC
INTERFACE
ISCL
ISDA
HSCL1
HSDA1
HSCL2
HSDA2
This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without
notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
Revision 0.9
-1-
April 2002
http://www.Datasheet4U.com
1 page  
MYSON-CENTURY
TECHNOLOGY
MTV412M
(Rev 0.9)
FUNCTIONAL DESCRIPTIONS
1. 8051 CPU Core
The CPU core of MTV412M is compatible with the industry standard 8051, which includes 256 bytes RAM,
Special F unction R egisters (SFR), two t imers, five interrupt s ources an d a s erial interface. The CPU c ore
fetches it s prog ram c ode f rom t he 1 28K bytes Flash i n M TV412M. It uses Por t0 and P ort2 to a ccess t he
“external special function register” (XFR) and external auxiliary RAM (AUXRAM).
The CPU core can run a t double rate when FclkE is set. Once the bit is set, the CPU runs as if a 2 4MHz
X’tal is applied on MTV412M, but the peripherals (IIC, DDC, H/V processor) still run at the original frequency.
Note: A ll reg isters listed in this do cument re side in 8 051’s ex ternal R AM area (XFR). For in ternal R AM
memory map, please refer to 8051 spec.
2. Memory Allocation
2.1 Internal Special Function Registers (SFR)
The SFR is a group of registers that are the same as standard 8051.
2.2 Internal RAM
There are total 256 bytes internal RAM in MTV412M, the same as standard 8052.
2.3 External Special Function Registers (XFR)
The XFR is a group of registers allocated in the 8051 external RAM area F00h - FFFh. These registers are
used for special functions. Programs can use "MOVX" instruction to access these registers.
2.4 Auxiliary RAM (AUXRAM)
There are t otal 256 bytes auxiliary RAM al located in the 8051 external RAM area 800h - 8F Fh. P rograms
can use "MOVX" instruction to access the AUXRAM.
2.5 Dual Port RAM (DDCRAM1 & DDCRAM2)
There are 2x256 bytes Dual Port RAM allocated in the 8051 external RAM area 900h - 9FFh & E00h - EFFh
for H/W auto transfer DDC. The external DDC1/2 Host can access the RAM as if two 24LC02 EEPROMs are
connected o nto the i nterface. T he HS CL1, HS DA1 p ins can a ccess D DCRAM1 d irectly. And the HS CL2,
HSDA2 pins c an ac cess DDCRAM2 direc tly. Progra ms c an a lso us e "M OVX" instruction to ac cess these
RAM.
FFh Internal RAM
SFR
Accessible by
indirect
addressing only
(Using
MOV A,@Ri
instruction)
80h
7Fh Internal RAM
Accessible by
direct addressing
Accessible by
direct and indirect
addressing
00h
FFFh
XFR
Accessible by
indirect external
RAM addressing
(Using MOVX
instruction)
F00h
8FFh
AUXRAM
Accessible by
indirect external
RAM addressing
(Using MOVX
instruction
800h
EFFh DDCRAM1
Accessible by
indirect external
RAM addressing
(Using MOVX
instruction)
E00h
9FFh
DDCRAM2
Accessible by
indirect external
RAM addressing
(Using MOVX
instruction)
900h
Revision 0.9
-5-
April 2002
5 Page 
MYSON-CENTURY
TECHNOLOGY
MTV412M
(Rev 0.9)
VSYNC
HSYNC
Digital Filter
Present
Check
Vpre
Polarity Check &
Freq. Count
Vfreq
Vpol
Vbpl
CVSYNC
XOR
Vself
Present
Check
CVpre
XOR VBLANK
Digital Filter
Polarity Check &
Sync Seperator
Hpol
Present Check &
Freq. Count
Composite
Pulse Insert
Hpre
Hfreq
Hbpl
XOR
XOR
HBLANK
H/V SYNC Processor Block Diagram
6.1 Composite SYNC separation/insertion
The MTV412M c ontinuously m onitors the input HSYNC. If the v ertical SY NC puls e can be extracted from
the input, a CVpre flag is set and users can select the extracted "CVSYNC" for the source of polarity check,
frequency c ount, and VBLANK out put. T he C VSYNC t hen ha s 8us d elay c ompared t o the original s ignal.
The MTV412M can also insert pulse to HBLANK output during composite VSYNC’s active time. The width of
insert pulse is 1/8 HSYNC period and the insertion frequency can adapt to original HSYNC. The insert pulse
of HBLANK can be disabled or enabled by setting “NoHins” control bit. If “NoHins” bit is set to "1", HBLANK
output will be same as HSYNC input (of course, polarity can be controlled by HBpl bit).
6.2 H/V Frequency Counter
MTV412M c an d iscriminate H SYNC/VSYNC frequency a nd s ave the in formation in XF Rs. The 14 -bit
Hcounter counts t he t ime of 64xHSYNC period, t hen l oads t he result int o t he H CNTH/HCNTL latch. T he
output value is then [(128000000/H-Freq) - 1] , updated onc e per V SYNC/CVSYNC p eriod w hen
VSYNC/CVSYNC is p resent o r continuously upd ated w hen VS YNC/CVSYNC is n on-present. T he 12 -bit
Vcounter counts the time between two V SYNC pulses, then loads the result i nto the VCNTH/VCNTL latch.
The ou tput v alue is then (625 00/V-Freq), u pdated ev ery V SYNC/CVSYNC p eriod. An ex tra ov erflow bit
indicates the condition of H/V counter overflow. T he VFchg/HFchg interrupt is set when VCNT/HCNT value
changes or ov erflows. Table 6 .2.1 an d T able 6. 2.2 show t he H CNT/VCNT v alue un der t he o perations o f
12MHz.
Revision 0.9
- 11 -
April 2002
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet MTV412M.PDF ] | |
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