PDF 845G Data sheet ( Hoja de datos )

Número de pieza	845G
Descripción	Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub
Fabricantes	Intel Corporation
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No Preview Available ! www.DataSheet.co.kr Intel® 845G/845GL/845GV Chipset Datasheet Intel® 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH) October 2002 Document Number: 290746-002 Datasheet pdf - http://www.DataSheet4U.net/ 1 page www.DataSheet.co.kr 3.5.3 3.5.4 3.5.2.9 HDR1—Header Type Register (Device 1).........................83 3.5.2.10 PBUSN1—Primary Bus Number Register (Device 1) .......83 3.5.2.11 SBUSN1—Secondary Bus Number Register (Device 1)...84 3.5.2.12 SUBUSN1—Subordinate Bus Number Register (Device 1).. 84 3.5.2.13 SMLT1—Secondary Bus Master Latency Timer Register (Device 1).............................................................................84 3.5.2.14 IOBASE1—I/O Base Address Register (Device 1)............85 3.5.2.15 IOLIMIT1—I/O Limit Address Register (Device 1).............85 3.5.2.16 SSTS1—Secondary Status Register (Device 1) ...............86 3.5.2.17 MBASE1—Memory Base Address Register (Device 1) ....87 3.5.2.18 MLIMIT1—Memory Limit Address Register (Device 1) .....88 3.5.2.19 PMBASE1—Prefetchable Memory Base Address Register (Device 1).............................................................................89 3.5.2.20 PMLIMIT1—Prefetchable Memory Limit Address Register (Device 1).............................................................................89 3.5.2.21 BCTRL1—Bridge Control Register (Device 1) ..................90 3.5.2.22 ERRCMD1—Error Command Register (Device 1)............91 Integrated Graphics Device Registers (Device 2) .............................92 3.5.3.1 VID2—Vendor Identification Register (Device 2) ..............93 3.5.3.2 DID2—Device Identification Register (Device 2)...............93 3.5.3.3 PCICMD2—PCI Command Register (Device 2) ...............94 3.5.3.4 PCISTS2—PCI Status Register (Device 2) .......................95 3.5.3.5 RID2—Revision Identification Register (Device 2) ............95 3.5.3.6 CC—Class Code Register (Device 2) ...............................96 3.5.3.7 CLS—Cache Line Size Register (Device 2) ......................96 3.5.3.8 MLT2—Master Latency Timer Register (Device 2) ...........96 3.5.3.9 HDR2—Header Type Register (Device 2).........................97 3.5.3.10 GMADR —Graphics Memory Range Address Register (Device 2).............................................................................97 3.5.3.11 MMADR—Memory Mapped Range Address Register (Device 2).............................................................................98 3.5.3.12 SVID2—Subsystem Vendor Identification Register (Device 2).............................................................................98 3.5.3.13 SID2—Subsystem Identification Register (Device 2) ........98 3.5.3.14 ROMADR—Video BIOS ROM Base Address Registers (Device 2).............................................................................99 3.5.3.15 CAPPOINT—Capabilities Pointer Register (Device 2)......99 3.5.3.16 INTRLINE—Interrupt Line Register (Device 2)..................99 3.5.3.17 INTRPIN—Interrupt Pin Register (Device 2) ...................100 3.5.3.18 MINGNT—Minimum Grant Register (Device 2) ..............100 3.5.3.19 MAXLAT—Maximum Latency Register (Device 2)..........100 3.5.3.20 PMCAPID—Power Management Capabilities ID Register (Device 2)...........................................................................100 3.5.3.21 PMCAP—Power Management Capabilities Register (Device 2)...........................................................................101 3.5.3.22 PMCS—Power Management Control/Status Register (Device 2)...........................................................................101 Device 6 Registers ..........................................................................102 3.5.4.1 DWTC—DRAM Write Throttling Control Register (Device 6)...........................................................................102 3.5.4.2 DRTC—DRAM Read Throttling Control Register (Device 6)...........................................................................103 4 Functional Description ...................................................................................105 4.1 Processor System Bus.................................................................................105 Intel® 82845G/82845GL/82845GV GMCH Datasheet 5 Datasheet pdf - http://www.DataSheet4U.net/ 5 Page www.DataSheet.co.kr Intel® 82845G GMCH Features I Host Interface Support I Integrated Graphics • One processor in a mPGA478 package • Hyper-Threading Technology support • 400/533 MHz PSB (100/133 MHz bus clock) — Core Frequency of 200 MHz — 3D Setup and Render Engine - Discrete Triangles, Strips and Fans Support - Indexed Vertex and Flexible Vertex Formats • PSB Dynamic Bus Inversion on the data bus • 32-bit addressing for access to 4 GB of memory space - Pixel Accurate Fast Scissoring and Clipping Operation - Backface Culling Support - Supports D3D and OGL Pixelization Rules • 8 deep In Order Queue - Anti-Aliased Lines Support • AGTL+ On-die Termination I System Memory Controller (SDR and DDR) — One, 64-bit wide SDR or DDR SDRAM data channel - Sprite Points Support — High Quality Texture Engine (see Section 1.4.5) — 3D Graphics Rasterization Enhancements (see Section 1.4.5) — Bandwidth up to 1 GB/s (SDR), and 2.1 GB/s (DDR266) — 2D Graphics (see Section 1.4.5) — Configurable to support either a DDR board or an SDR board — 64-Mb, 128-Mb, 256-Mb, and 512-Mb SDRAM technologies — Supports only x8 and x16 SDRAM devices with four — Video DVD/PC-VCR (see Section 1.4.5) — Video Overlay (see Section 1.4.5) I Analog Display Support — 350 MHz Integrated 24-bit RAMDAC banks — Up to 2048x1536 at 60 Hz refresh — Unbuffered, unregistered 184-pin non-ECC DDR — Hardware Color Cursor Support SDRAM DIMMs only — DDC2B Compliant Interface — Opportunistic refresh I Digital Display Channels — Up to 16, simultaneously open pages — Two channels multiplexed with AGP — SPD (Serial Presence Detect) scheme for DIMM detection — Suspend-to-RAM support using CKE — Double Data Rate (DDR) SDRAM Configuration — 165 MHz dot clock on each 12-bit interface — Can combine two, 12-bit channels to form one 24-bit interface: Supports flat panels up to 2048x1536 at 60 Hz or dCRT/HDTV at 1920x1080 at 85 Hz - Up to 2.0 GB of 200 MHz or 266 MHz DDR SDRAM — Supports Hot Plug and Display - Two DDR DIMMs, single-sided and/or double-sided - DDR200/266 unregistered, 184-pin non-ECC DDR SDRAM DIMMs - JEDEC DDR DIMM specification configurations only - Does not support double-sided x16 DDR DIMMs - Selective Command-Per-Clock (selective CPC) accesses. — Supports LVDS, TMDS transmitters or TV-out encoders — ADD card utilizes AGP connector — Three Display Control interfaces (I2C/DDC) multiplexed on AGP I Hub Interface — Supports Hub Interface 1.5 — Single Data Rate (SDR) SDRAM Configuration - Up to 2.0 GB of 133 MHz SDR SDRAM - Up to two SDR DIMMs, single-sided and/or double-sided - PC133 unregistered 168-pin non-ECC SDR SDRAM DIMMs - Does not support PC100 - Mixed-mode/uneven double-sided SDR DIMMs not supported - 3.3 V SDR DIMM configurations only — 266 MB/s point-to-point Hub Interface to the ICH4 — 66 MHz base clock — 1.5 V operation I GMCH Package — 37.5 mm x 37.5 mm FC-BGA package with 1 mm ball pitch I AGP Interface — Supports a single 1.5 V Accelerated Graphics Port Interface, Specification 2.0-compliant device — Supports 1X/2X/4X data transfers and 2X/4X Fast Writes — 32-deep AGP request queue — AGP signals muxed with two Intel® DVO ports: Supports ADD cards Intel® 82845G/82845GL/82845GV GMCH Datasheet 11 Datasheet pdf - http://www.DataSheet4U.net/ 11 Page

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