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WPC8765L 반도체 회로 부품 판매점

(WPC8765L / WPC8769L) Mobile Embedded Controller



Nuvoton Technology 로고
Nuvoton Technology
WPC8765L 데이터시트, 핀배열, 회로
Product Brief
June 2008
Revision 1.2
WPC8765L / WPC8769L Mobile Embedded Controller with
SPITM Flash Interface and MC-Compliant CIR Port
(Revisions A4 and A5)
General Description
The Nuvoton WPC8765L and WPC8769L are highly inte-
grated embedded controllers (EC) with an embedded RISC
core and integrated advanced functions. They are targeted
for a wide range of portable applications.
The WPC8765L/WPC8769L incorporate the CompactRISC®
CR16CPlus core (a high-performance 16-bit RISC proces-
sor), on-chip ROM and RAM memories, system support func-
tions and a Flash Interface Unit (FIU) that interfaces directly
with external SPI flash memory devices.
System support functions include: watchdog, PWM, timers,
interrupt control, General-Purpose I/O (GPIO) with internal
keyboard matrix scanning, PS/2® interface, SMBus® inter-
face, UART, SPI, high-accuracy analog-to-digital (ADC)
and digital-to-analog (DAC) converters for battery charging,
system control, system health monitoring and analog con-
trols, and a SensorPathinterface.
The WPC8765L/WPC8769L interface with the host via an
LPC interface.The WPC8765L/WPC8769L are PC01 and
ACPI compliant, and offer a single-chip solution for the most
commonly used notebook PC I/O peripherals.
Outstanding Features
Shared BIOS flash memory
Support for SPI flash memories
Flash page programing support
MC-compliant Consumer Infrared (CIR) Port
High-accuracy, high-speed ADC
Up to 88 GPIO ports (including keyboard scanning)
with a variety of wake-up events
16-bit RISC core, with up to 4 Mbytes of external ad-
dress space, running at up to 25 MHz
128-pin LQFP package
System Block Diagram
South Bridge
Main Analog Standby Backup Battery
VDD VCC VCC VBAT
Shared Flash
SPI
Battery
Panel
Temp Sensor
Switch Pad
and LEDs
Charger
Brightness
Contrast
2 x SMBus
SPI
A/D and D/A
D/A
WPC8765L/WPC8769L
12 x 8 - 18 x 8 Keyboard Matrix
3 x PS2
PWM
Tacho
Keyboard
Touch Pad
Mouse
3 x Fan
CIR JTAG
© 2008 Nuvoton Technology Corporation
www.nuvoton.com


WPC8765L 데이터시트, 핀배열, 회로
Device-Specific Information
The following table shows the main differences between Revisions A4 and A5 of the WPC8765L and WPC8769L device.
Feature
Revision A4
WPC8765L WPC8769L
Revision A5
WPC8769LA0
ADC Resolution
PWM Outputs
10 bit
3
8 bit
8 bit
8
Features
Embedded Controller Features
Processing Unit
CompactRISC CR16CPlus 16-bit embedded RISC
processor core (the “core”)
Up to 4 Mbytes of external address space
Internal Memory
1 Kbyte of ROM
4 Kbytes of on-chip RAM
All memory types can hold both code and data
Flash Interface Unit (FIU)
Up to 4 Mbytes of code and data
Hardware-protected boot zone block protection
SPI External Memory
Up to 32 Mbits
Fast Read mode
Page programing support
Configurable clock rate
Field upgradeable
Shared Memory Controller (SHM)
Supports BIOS (flash) memory sharing with PC host
Supports host-controlled code download and update
Memory access protection
LPC System Interface
Based on Intel’s LPC Interface Specification Revision
1.1, August 2002
Four optional 8-bit DMA channels
I/O, Memory and 8-bit Firmware Memory read and write
cycles, Firmware Memory writes may insert wait cycles
Bootable Memory Support
Base Address (BADDR1-0) straps to determine the
base address of the index-data register pair
Alternate base address configurable by the core
LPCPD and CLKRUN support
Embedded Controller System Features
Host Interface
Comprises host interface channels, typically used
for KBC and ACPI Private or Shared EC channels
8042 KBC-standard interface (legacy 60h, 64h)
Two PM interface ports (legacy 62h, 66h; 68h, 6Ch)
ACPI EC with either Shared or Private interface
through the PM interface
Two Mailbox areas for host-core communication, up
to 4 Kbytes each; maximum 4 Kbytes total
Generates IRQ, SMI and SCI
Provides IRQ1 and IRQ12 support
Provides Fast Gate A20 and Fast Host reset via firmware
Interrupt Control Unit (ICU)
31 maskable vectored interrupts (of which eight are
external)
General-purpose external interrupt inputs through
MIWU
Enable and pending indication for each interrupt
Non-maskable interrupt input
Multi-Input Wake-Up (MIWU)
Up to 40 wake-up or interrupt inputs
Generates wake-up event to PMC (Power Manage-
ment Controller)
Generates interrupts to ICU
User-selectable trigger conditions
Internal Keyboard Matrix Scanning
Up to 18 open-collector outputs (at least 12)
Eight Schmitt inputs with internal pull-ups
General-Purpose I/O (GPIO) Ports
64 port pins
I/O pins individually configured as input or output
Configurable internal pull-up / pull-down resistors
Outputs individually configured as push-pull or
open-drain
Two echo inputs with wake-enabled interrupts
Additional 12 GPIOs with wake-enabled interrupts
Four GPIOs capable of 20 mA sink current
Seven GPIOs are accessible to the host
Optional low-cost external GPIO expansion through
the SensorPath interface
PS/2 Interface
Three external ports: can be used for keyboard,
mouse and an additional pointing device
Byte-level handling via hardware accelerator
www.nuvoton.com
2
Revision 1.2




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(WPC8765L / WPC8769L) Mobile Embedded Controller - Nuvoton Technology