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PDF SX20AC Data sheet ( Hoja de datos )
| Número de pieza | SX20AC | |
| Descripción | (SX20AC / SX28AC) Configurable Communications Controllers | |
| Fabricantes | Ubicom | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de SX20AC (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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March, 2002
SX20AC/SX28AC
Configurable Communications Controllers with EE/Flash Program
Memory, In-System Programming Capability and On-Chip Debug
1.0 PRODUCT OVERVIEW
1.1 Introduction
www.DataShTehete4UU.cbomicom SX family of configurable communications
controllers are fabricated in an advanced CMOS process
technology. The advanced process, combined with a
RISC-based architecture, allows high-speed computa-
tion, flexible I/O control, and efficient data manipulation.
Throughput is enhanced by operating the device at fre-
quencies up to 75 MHz and by optimizing the instruction
set to include mostly single-cycle instructions. In addition,
the SX architecture is deterministic and totally reprogra-
mable. The unique combination of these characteristics
enables the device to implement hard real-time functions
as software modules (Virtual Peripheral™) to replace tra-
ditional hardware functions.
On-chip functions include a general-purpose 8-bit timer
with prescaler, an analog comparator, a brown-out detec-
tor, a watchdog timer, a power-save mode with multi-
source wakeup capability, an internal R/C oscillator, user-
selectable clock modes, and high-current outputs.
OSC1 OSC2
RTCC
OSC
Driver
4MHz
Clock
Select
8-bit Watchdog
Timer (WDT)
8-bit Timer
RTCC
Internal
RC OSC
÷ 4 or ÷ 1
System Clock
Power-On
Reset
Brown-Out
MCLR
Prescaler for RTCC
RESET
or
Prescaler for WDT
Interrupt
MIWU System
Clock
Internal Data Bus
Interrupt Stack
MIWU
8
3 Analog
Port B
Comp
88
8
8
Instruction
Pipeline
Fetch
Decode
Executive
Write Back
PC
3 Level
Stack
8
W
FSR
PC
STATUS
OPTION
8
8
8
Address
88
ALU
136 Bytes
SRAM
Address 12
In-System
Debugging
In-System
Programming
2k Words
EEPROM
88
Port A Port C
48
MODE
8 Write Data
8 Read Data
12 Instruction
IREAD
Figure 1-1. Block Diagram
Ubicom™ and the Ubicom logo are trademarks of Ubicom, Inc.
I2C™ is a trademark of Philips Corporation
© 2002 Ubicom, Inc. All rights reserved.
All other trademarks mentioned in this document are property of their respec-
tive companies.
- 1 - www.ubicom.com
1 page  
SX20AC/SX28AC
2.0 CONNECTION DIAGRAMS
2.1 Pin Assignments
www.DataSheet4U.com
SX 28-PIN
SX 20-PIN
RA2
RA3
RTCC
MCLR
Vss
Vss
RB0
RB1
RB2
RB3
1
2
3
4
5
6
7
8
9
10
20 RA1
19 RA0
18 OSC1
17 OSC2
16 Vdd
15 Vdd
14 RB7
13 RB6
12 RB5
11 RB4
SSOP
RTCC
Vdd
n.c.
Vss
n.c.
RA0
RA1
RA2
RA3
RB0
RB1
RB2
RB3
RB4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 MCLR
27 OSC1
26 OSC2
25 RC7
24 RC6
23 RC5
22 RC4
21 RC3
20 RC2
19 RC1
18 RC0
17 RB7
16 RB6
15 RB5
DIP
SX 28-PIN
Vss
RTCC
Vdd
Vdd
RA0
RA1
RA2
RA3
RB0
RB1
RB2
RB3
RB4
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 MCLR
27 OSC1
26 OSC2
25 RC7
24 RC6
23 RC5
22 RC4
21 RC3
20 RC2
19 RC1
18 RC0
17 RB7
16 RB6
15 RB5
SSOP
2.2 Pin Descriptions
Name Pin Type Input Levels
Description
RA0 I/O TTL/CMOS Bidirectional I/O Pin; symmetrical source / sink capability
RA1 I/O TTL/CMOS Bidirectional I/O Pin; symmetrical source / sink capability
RA2 I/O TTL/CMOS Bidirectional I/O Pin; symmetrical source / sink capability
RA3 I/O TTL/CMOS Bidirectional I/O Pin; symmetrical source / sink capability
RB0 I/O TTL/CMOS/ST Bidirectional I/O Pin; comparator output; MIWU/Interrupt input
RB1 I/O TTL/CMOS/ST Bidirectional I/O Pin; comparator negative input; MIWU/Interrupt input
RB2 I/O TTL/CMOS/ST Bidirectional I/O Pin; comparator positive input; MIWU/Interrupt input
RB3 I/O TTL/CMOS/ST Bidirectional I/O Pin; MIWU/Interrupt input
RB4 I/O TTL/CMOS/ST Bidirectional I/O Pin; MIWU/Interrupt input
RB5 I/O TTL/CMOS/ST Bidirectional I/O Pin; MIWU/Interrupt input
RB6 I/O TTL/CMOS/ST Bidirectional I/O Pin; MIWU/Interrupt input
RB7 I/O TTL/CMOS/ST Bidirectional I/O Pin; MIWU/Interrupt input
RC0 I/O TTL/CMOS/ST Bidirectional I/O pin
RC1 I/O TTL/CMOS/ST Bidirectional I/O pin
RC2 I/O TTL/CMOS/ST Bidirectional I/O pin
RC3 I/O TTL/CMOS/ST Bidirectional I/O pin
RC4 I/O TTL/CMOS/ST Bidirectional I/O pin
RC5 I/O TTL/CMOS/ST Bidirectional I/O pin
RC6 I/O TTL/CMOS/ST Bidirectional I/O pin
RC7 I/O TTL/CMOS/ST Bidirectional I/O pin
RTCC
I
ST Input to Real-Time Clock/Counter
MCLR
I
ST Master Clear reset input – active low
OSC1/In/Vpp
I
ST Crystal oscillator input – external clock source input
OSC2/Out
O
CMOS
Crystal oscillator output – in R/C mode, internally pulled to Vdd through weak
pull-up
Vdd P
– Positive supply pin
Vss P
– Ground pin
Note: I = input, O = output, I/O = Input/Output, P = Power, TTL = TTL input, CMOS = CMOS input,
ST = Schmitt Trigger input, MIWU = Multi-Input Wakeup input
© 2002 Ubicom, Inc. All rights reserved.
-5-
www.ubicom.com
5 Page 
SX20AC/SX28AC
4.0 SPECIAL-FUNCTION REGISTERS
The CPU uses a set of special-function registers to con-
trol the operation of the device.
The CPU registers include an 8-bit working register (W),
which serves as a pseudo accumulator. It holds the sec-
ond operand of an instruction, receives the literal in
immediate type instructions, and also can be program-
selected as the destination register.
A set of 31 file registers serves as the primary accumula-
tor. One of these registers holds the first operand of an
instruction and another can be program-selected as the
destination register. The first eight file registers include
the Real-Time Clock/Counter register (RTCC), the lower
eight bits of the 11-bit Program Counter (PC), the 8-bit
STATUS register, three port control registers for Port A,
www.DataShPeeotr4tUB.c,omPort C, the 8-bit File Select Register (FSR), and
INDF used for indirect addressing.
The five low-order bits of the FSR register select one of
the 31 file registers in the indirect addressing mode. Call-
ing for the file register located at address 00h (INDF) in
any of the file-oriented instructions selects indirect
addressing, which uses the FSR register. It should be
noted that the file register at address 00h is not a physi-
cally implemented register. The CPU also contains an 8-
level, 11-bit hardware push/pop stack for subroutine link-
age.
Table 4-1. Special-Function Registers
Addr Name
00h INDF
01h RTCC
02h PC
03h STATUS
04h FSR
05h RA
06h RB
07h RC*
Function
Used for indirect addressing
Real Time Clock/Counter
Program Counter (low byte)
Holds Status bits of ALU
File Select Register
Port RA Control register
Port RB Control register
Port RC Control register
*In the SX18 package, Port C is not used, and address
07h is available as a general-purpose RAM location.
4.1 PC Register (02h)
The PC register holds the lower eight bits of the program
counter. It is accessible at run time to perform branch
operations.
4.2 STATUS Register (03h)
The STATUS register holds the arithmetic status of the
ALU, the page select bits, and the reset state. The
STATUS register is accessible during run time, except
that bits PD and TO are read-only. It is recommended
that only SETB and CLRB instructions be used on this
register. Care should be exercised when writing to the
STATUS register as the ALU status bits are updated
upon completion of the write operation, possibly leaving
the STATUS register with a result that is different than
intended.
PA2 PA1 PA0 TO PD Z DC C
Bit 7
Bit 0
Bit 7-5: Page select bits PA2:PA0
000 = Page 0 (000h – 01FFh)
001 = Page 1 (200h – 03FFh)
010 = Page 2 (400h – 05FFh)
011 = Page 3 (600h – 07FFh)
Bit 4: Time Out bit, TO
1 = Set to 1 after power up and upon exe-
cution of CLRWDT or SLEEP instructions
0 = A watchdog time-out occurred
Bit 3: Power Down bit, PD
1= Set to a 1 after power up and upon ex-
ecution of the CLRWDT instruction
0 = Cleared to a ‘0’ upon execution of
SLEEP instruction
Bit 2: Zero bit, Z
Bit 1:
1 = Result of math operation is zero
0 = Result of math operation is non-zero
Digit Carry bit, DC
After Addition:
1 = A carry from bit 3 occurred
0 = No carry from bit 3 occurred
After Subtraction:
1 = No borrow from bit 3 occurred
0 = A borrow from bit 3 occurred
Bit 0: Carry bit, C
After Addition:
1 = A carry from bit 7 of the result occurred
0 = No carry from bit 7 of the result oc-
curred
After Subtraction:
1 = No borrow from bit 7 of the result oc-
curred
0 = A borrow from bit 7 of the result oc-
curred
Rotate (RR or RL) Instructions:
The carry bit is loaded with the low or high
order bit, respectively. When CF bit is
cleared, Carry bit works as input for ADD
and SUB instructions.
© 2002 Ubicom, Inc. All rights reserved.
- 11 -
www.ubicom.com
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SX20AC.PDF ] | |
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