|
|
PDF N80C42 Data sheet ( Hoja de datos )
| Número de pieza | N80C42 | |
| Descripción | UNIVERSAL PERIPHERAL INTERFACE CHMOS 8-BIT SLAVE MICROCONTROLLER | |
| Fabricantes | Intel Corporation | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de N80C42 (archivo pdf) en la parte inferior de esta página. Total 25 Páginas | ||
|
No Preview Available !
UPI-C42 UPI-L42
UNIVERSAL PERIPHERAL INTERFACE
CHMOS 8-BIT SLAVE MICROCONTROLLER
Y Pin Software and Architecturally
Compatible with all UPI-41 and UPI-42
Products
Y Low Voltage Operation with the UPI-
L42
Full 3 3V Support
Y Hardware A20 Gate Support
Y Suspend Power Down Mode
Y
www.DataSheet4U.com
Security Bit Code Protection Support
Y 8-Bit CPU plus ROM OTP EPROM RAM
I O Timer Counter and Clock in a
Single Package
Y 4096 x 8 ROM OTP 256 x 8 RAM 8-Bit
Timer Counter 18 Programmable I O
Pins
Y DMA Interrupt or Polled Operation
Supported
Y One 8-Bit Status and Two Data
Registers for Asynchronous Slave-to-
Master Interface
Y Fully Compatible with all Intel and Most
Other Microprocessor Families
Y Interchangeable ROM and OTP EPROM
Versions
Y Expandable I O
Y Sync Mode Available
Y Over 90 Instructions 70% Single Byte
Y Quick Pulse Programming Algorithm
Fast OTP Programming
Y Available in 40-Lead Plastic 44-Lead
Plastic Leaded Chip Carrier and
44-Lead Quad Flat Pack Packages
(See Packaging Spec Order 240800 Package Type P N
and S)
The UPI-C42 is an enhanced CHMOS version of the industry standard Intel UPI-42 family It is fabricated on
Intel’s CHMOS III-E process The UPI-C42 is pin software and architecturally compatible with the NMOS UPI
family The UPI-C42 has all of the same features of the NMOS family plus a larger user programmable memory
array (4K) hardware A20 gate support and lower power consumption inherent to a CHMOS product
The UPI-L42 offers the same functionality and socket compatibility as the UPI-C42 as well as providing low
voltage 3 3V operation
The UPI-C42 is essentially a ‘‘slave’’ microcontroller or a microcontroller with a slave interface included on the
chip Interface registers are included to enable the UPI device to function as a slave peripheral controller in the
MCS Modules and iAPX family as well as other 8- 16- and 32-bit systems
To allow full user flexibility the program memory is available in ROM and One-Time Programmable EPROM
(OTP)
290414 – 1
Figure 1 DIP Pin
Configuration
290414 – 2
Figure 2 PLCC Pin Configuration
290414 – 3
Figure 3 QFP Pin Configuration
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT INTEL CORPORATION 1996
December 1995
Order Number 290414-003
1 page  
UPI-C42 UPI-L42
UPI-42 COMPATIBLE FEATURES
1 Two Data Bus Buffers one for input and one for
output This allows a much cleaner Master Slave
protocol
www.DataSheet4U.com
290414 – 5
2 8 Bits of Status
ST7 ST6 ST5 ST4 F1 F0 IBF OBF
D7 D6 D5 D4 D3 D2 D1 D0
ST4 – ST7 are user definable status bits These
bits are defined by the ‘‘MOV STS A’’ single
byte single cycle instruction Bits 4–7 of the
acccumulator are moved to bits 4–7 of the status
register Bits 0–3 of the status register are not
affected
MOV STS A Op Code 90H
1 001000 0
D7 D0
3 RD and WR are edge triggered IBF OBF F1 and
INT change internally after the trailing edge of RD
or WR
During the time that the host CPU is reading the
status register the UPI is prevented from updat-
ing this register or is ‘locked out ’
290414 – 6
4 P24 and P25 are port pins or Buffer Flag pins
which can be used to interrupt a master proces-
sor These pins default to port pins on Reset
If the ‘‘EN FLAGS’’ instruction has been execut-
ed P24 becomes the OBF (Output Buffer Full)
pin A ‘‘1’’ written to P24 enables the OBF pin (the
pin outputs the OBF Status Bit) A ‘‘0’’ written to
P24 disables the OBF pin (the pin remains low)
This pin can be used to indicate that valid data is
available from the UPI (in Output Data Bus Buff-
er)
If ‘‘EN FLAGS’’ has been executed P25 be-
comes the IBF (Input Buffer Full) pin A ‘‘1’’ writ-
ten to P25 enables the IBF pin (the pin outputs
the inverse of the IBF Status Bit A ‘‘0’’ written to
P25 disables the IBF pin (the pin remains low)
This pin can be used to indicate that the UPI is
ready for data
Data Bus Buffer Interrupt Capability
290414 – 7
EN FLAGS Op Code 0F5H
1 111010 1
D7 D0
5 P26 and P27 are port pins or DMA handshake
pins for use with a DMA controller These pins
default to port pins on Reset
If the ‘‘EN DMA’’ instruction has been executed
P26 becomes the DRQ (DMA Request) pin A ‘‘1’’
written to P26 causes a DMA request (DRQ is
activated) DRQ is deactivated by DACKRD
DACKWR or execution of the ‘‘EN DMA’’ in-
struction
DMA Handshake Capability
290414 – 8
5
5 Page 
UPI-C42 UPI-L42
b Apply access code to appropriate inputs to put
the device into security mode
c Apply high voltage to EA and VDD pins
d Follow the programming procedure as per the
Quick-Pulse Programming Algorithm with known
data on the databus Not only the security bit but
also the security byte of the signature row is pro-
grammed
e Verify that the security byte of the signature
mode contains the same data as appeared on
the data bus (If DB0 – DB7 e high the security
byte will contain FFH )
f
www.DataSheet4U.com
Read two consecutive known bytes from the
EPROM array and verify that the wrong data are
retrieved in at least one verification If the
EPROM can still be read the security bit may
have not been fully programmed though the se-
curity byte in the signature mode has
Verification
Since the security bit address overlaps the address
of the security byte of the signature mode it can be
used to check indirectly whether the security bit has
been programmed or not Therefore the security bit
verification is a mere read operation of the security
byte of the signature row (0FFH e security bit pro-
grammed 00H e security bit unprogrammed) Note
that during the security bit programming the reading
of the security byte does not necessarily indicate
that the security bit has been successfully pro-
grammed Thus it is recommended that two consec-
utive known bytes in the EPROM array be read and
the wrong data should be read at least once be-
cause it is highly improbable that random data coin-
cides with the correct ones twice
SIGNATURE MODE
The UPI-C42 has an additional 64 bytes of EPROM
available for Intel and user signatures and miscella-
neous purposes The 64 bytes are partitioned as fol-
lows
A Test code checksum This can accommodate
up to 25 bytes of code for testing the internal
nodes that are not testable by executing from the
external memory The test code checksum is
present on ROMs and OTPs
B Intel signature This allows the programmer to
read from the UPI-41AH 42AH C42 the manu-
facturer of the device and the exact product
name It facilitates automatic device identification
and will be present in the ROM and OTP ver-
sions Location 10H contains the manufacturer
code For Intel it is 89H Location 11H contains
the device code
The code is 43H and 42H for the 8042AH 80C42
and OTP 8742AH 87C42 respectively The
code is 44H for any device with the security bit
set by Intel
C User signature The user signature memory is
implemented in the EPROM and consists of 2
bytes for the customer to program his own signa-
ture code (for identification purposes and quick
sorting of previously programmed materials)
D Test signature This memory is used to store
testing information such as test data bin num-
ber etc (for use in quality and manufacturing
control)
E Security byte This byte is used to check
whether the security bit has been programmed
(see the security bit section)
F UPI-C42 Intel Signature Applies only to
CHMOS device Location 20H contains the man-
ufacturer code and location 21H contains the de-
vice code The Intel UPI-C42 manufacturer’s
code is 99H The device ID’s are 82H for the
OTP version and 83H for the ROM version The
device ID’s are the same for the UPI-L42
The signature mode can be accessed by setting
P10 e 0 P11 – P17 e 1 and then following the pro-
gramming and or verification procedures The loca-
tion of the various address partitions are as shown in
Table 3
SYNC MODE
The Sync Mode is provided to ease the design of
multiple controller circuits by allowing the designer
to force the device into known phase and state time
The Sync Mode may also be utilized by automatic
test equipment (ATE) for quick easy and efficient
synchronizing between the tester and the DUT (de-
vice under test)
Sync Mode is enabled when SS pin is raised to high
voltage level of a12 volts To begin synchroniza-
tion T0 is raised to 5 volts at least four clock cycles
after SS T0 must be high for at least four X2 clock
cycles to fully reset the prescaler and time state
generators T0 may then be brought down during
low state of X2 Two clock cycles later with the ris-
ing edge of X2 the device enters into Time State 1
Phase 1 SS is then brought down to 5 volts 4 clocks
later after T0 RESET is allowed to go high 5 tCY (75
clocks) later for normal execution of code
11
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet N80C42.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| N80C42 | UNIVERSAL PERIPHERAL INTERFACE CHMOS 8-BIT SLAVE MICROCONTROLLER | Intel Corporation |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |