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PDF COM20051I Data sheet ( Hoja de datos )
| Número de pieza | COM20051I | |
| Descripción | Integrated Microcontroller and ARCNET (ANSI 878.1) Interface | |
| Fabricantes | SMSC Corporation | |
| Logotipo |  |
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COM20051I
Integrated Microcontroller and
ARCNET (ANSI 878.1) Interface
!" High Performance/Low Cost
!" Microcontroller Based on Popular 8051
Architecture
!" Intel 8051 Instruction Set Compatible
!" Drop-In Replacement for 80C32 PLCC
!" Network Supports up to 255 Nodes
!" Powerful Network Diagnostics
!" Maximum 507 Byte Packets
!" Duplicate Node ID Detection
!" Self-Configuring Network Protocol
FEATURES
!" Retains all 8051 Peripherals Including Serial I/O
and Two Timers
!" Utilizes ARCNET Token Bus Network Engine
!" Requires No Special Emulators
!" 5 Mbps to 156 Kbps Network Data Rate
!" Network Interface Supports RS-485, Twisted Pair,
Coaxial, and Fiber Optic Interfaces
!" Receive All Mode Allows Any Packet to Be
Received
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GENERAL DESCRIPTION
The COM20051I is a low-cost, highly-integrated microcontroller incorporating a high-performance network controller
based on the ARCNET Token Bus Standard (ANSI 878.1). The COM20051I is based around the popular Intel 8051
architecture. The device is implemented using a microcontroller core compatible with the Intel 80C32 ROMless
version of the 8051 architecture. The COM20051I is ideal for distributed control networking applications such as
those found in industrial/machine controls, building/factory automation, consumer products, instrumentation and
automobiles.
The COM20051I contains many features that are beneficial for embedded control applications. The microcontroller is
a fully-functional 16MHz 80C32 that is comparable to the Intel 80C32 with 2 timers. In contrast to other embedded
controller/networking solutions, the COM20051I adds a fully-featured, robust, powerful, and simple network interface
while retaining all of the basic 8051 peripherals, such as the serial port and counter/timers.
In addition, the COM20051I supports an Emulation Mode that permits the use of a standard 80C32 emulator in
conjunction with the COM20051I to develop software drivers for the network core. ARCNET core is mapped to a
256-byte page of the External Data Memory Space of the 80C32. This provides for an easy interface between the
CPU and the ARCNET core. The networking core is based around an ARCNET Token Bus protocol engine
that provides highly-reliable and fault tolerant message delivery at data rates ranging from 5Mbps down to 156
Kbps with message sizes varying from 0 to 507 bytes. The ARCNET protocol offers a simple, standardized, and
easily-understood networking solution for any application. The network interface supports several media interfaces,
including RS-485, coaxial, and twisted pair in either bus or star topologies. The network interface incorporates
powerful diagnostic features for network management and fault isolation. These include duplicate node ID detection,
reconfiguration detection, receive all (monitor) mode, receiver activity, and token detection.
ORDERING INFORMATION
Order Number: COM20051ILJ P
44 Pin PLCC Package
SMSC DS – COM20051I
Rev. 03/27/2000
1 page  
OVERVIEW
The COM20051I is essentially a network board-in-a-chip. It takes an 80C32 microcontroller core and an ARCNET
controller and integrates them into a single device. ARCNET is a token passing-based protocol that combines
powerful flow control, error detection, and diagnostic capabilities to deliver fast and reliable messages. The
COM20051I supports a variety of data rates (5 Mbps to 156 Kbps), topologies (bus, star, tree), and media types (RS-
485, coax, twisted pair, fiber optic, and powerline) to suit any type of application.
The ARCNET network core of the COM20051I contains many features that make network development simple and
easy to comprehend. Diagnostic features, such as Receive All, Duplicate ID Detection, Reconfiguration Detection,
Token, and Receiver Detection, all combine to make the COM20051I simple to use and to implement in any
environment. The ARCNET protocol itself is relatively simple to understand and very flexible. A wide variety of
support products are available to assist in network development, such as software drivers, line drivers, boards, and
development kits. The COM20051I implements a full-featured 16MHz, Intel-compatible 80C32 microcontroller with all
of the standard peripheral functions, including a full duplex serial port, two timer/counters, one 8-bit general purpose
digital I/O port, and interrupt controller. The 8051 architecture has long been a standard in the embedded control
industry for low-level data acquisition and control. ARCNET and the 8051 form a simple solution for many of today's
and tomorrow's low-level networking solutions.
In addition to the 80C32 and the ARCNET network core, the COM20051I contains all the address decoding and
interrupt routing logic to interface the network core to the 80C32 core. The integrated 8051/ARCNET combination
provides an extremely cost-effective and space-efficient solution for industrial networking applications. The
COM20051I can be used in a stand-alone embedded application, executing control algorithms or performing data
acquisition and communicating data in a master/slave or peer-to-peer configuration, or used as a slave processor
handling communication tasks in a multi-processing system.
PIN NO.
NAME
DESCRIPTION OF PIN FUNCTIONS
SYMBOL
DESCRIPTION
1
Receive In
RXIN
Input. Network receiver input.
2-9 P1.0-1.7 P1.0-1.7 Input/Output. Port 1 of the 8051. General purpose
digital I/O port.
10 Reset
RESET
Input. Active high reset.
11 P3.0
P3.0
Input/Output. Port 3 bit 0 of the 8051. RX input of
serial port.
12
nPulse 1
nPULSE1
Output. Network output. Open-drain when
backplane mode is invoked, otherwise it is a push-
pull output.
13-19
P3.1-3.7
P3.1-3.7
Input/Output. Port 3 bits 1-7 of the 8051.
20, 21
Crystal Oscillator XTAL1,
XTAL2
Input. Oscillator inputs 1 and 2.
22 Ground
VSS
Ground pin.
23
nPulse 2
nPULSE2
Output. Network output. Outputs a synchronous
clock at 2x the data rate when backplane mode is
invoked.
24-31
P2.0-2.7
P2.0-2.7
Input/Output. Port 2 of the 8051. High order address
bus.
32 nProgram Store nPSEN
Enable
Output.
33 Address Latch ALE
Enable
Output.
34 Transmit Enable TXEN
Output. This signal is used to enable the drivers for
transmitting. The polarity of this signal is
programmable by grounding the nPULSE2 pin prior
to the POWER-UP.
nPULSE2 floating prior to the power-up = TXEN
active high
nPULSE2 grounded prior to the power-up = TXEN
active low. (This option is available only in the
Backplane mode).
SMSC DS – COM20051I
Page 5
Rev. 03/27/2000
5 Page 
COM20051I MEMORY MAPPING
The COM20051I maps the Arcnet core into a 256 byte page of data memory space. This memory is physically
located internally to the device and itrquote s default base address on power up is 0000h. This 256 byte page can be
logically located anywhere within the 64K external data memory space while physically remaining on board. The
location of this 256 byte page is pointed to by the Address Decode Register in the device. This Address Decode
Register holds the upper 8 bits of the 16 bit address at which the 256 byte page boundary will start. The address of
this Address Decode Register is FFFFh. This register is also logically located in external data memory space but
physically located on the device. This register must be written to on power-up to properly locate the Arcnet core. .
The user must ensure that the Arcnet corerquote s 256 byte page does not conflict with external memory, otherwise
data bus contention will result. As an example, if the user has 32K of external data memory located from 0000h to
7FFFh then the Arcnet core should be mapped above this area, 8000H is suggested. The user will write 80h to
address FFFFh on power up to properly map the core to this location.
ARCNET Network Core - Overview and Architecture
ARCNET is a baseband token passing network protocol (ANSI 878.1). ARCNET features deterministic behavior,
hardware-based network configuration, flexible topologies, several data rates, and multiple media support. Data
rates varying from 5 Mbps to 156 Kbps and message sizes from 0 to 507 bytes are supported. Supported media
includes RS-485, twisted pair, coax, fiber optic, and powerline in bus, star or tree topologies. ARCNET has enjoyed
widespread use in the industrial community, finding a home in such applications as I/O control/acquisition, multi-
processor communications, point-of-sale terminals, in-vehicle navigation systems, data acquisition systems, remote
sensing, avionics, machine control, embedded computing, building automation, robotics, consumer products, and
security systems.
The ARCNET core used in the COM20051I is similar in architecture to SMSC's 200XX series of Industrial ARCNET
Controllers. The ARCNET core of the COM20051I contains a 1K x 8 internal RAM for packet buffering, Duplicate ID
Detection, Receive All Mode, New Next ID Indicator, Excessive NACK Interrupt, Programmable Data Rates,
Backplane Mode, Programmable Transmitter Enable, Polarity Receive Activity, Reconfiguration, Token Seen
Indicators, and Network Mapping hooks. The ARCNET core of the COM20051I uses a software-programmable node
ID, enabling the user to program the Node ID according to the application needs. The Node ID can be stored in an
electronic medium or changed with the switch.
SMSC DS – COM20051I
Page 11
Rev. 03/27/2000
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet COM20051I.PDF ] | |
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