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PDF KL5KUSB220 Data sheet ( Hoja de datos )
| Número de pieza | KL5KUSB220 | |
| Descripción | USB2.0 to 100 Ethernet Controller | |
| Fabricantes | Kawasaki | |
| Logotipo |  |
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KL5KUSB220
General Description
USB2.0 to 100 Ethernet Controller
The Kawasaki KL5KUSB220 Controller used in conjunction with the KL5KUSB200/201 USB2.0
transceiver is a unique solution to interface peripheral devices to the Universal Serial Bus 2.0
(USB2.0) and 100Base-T Ethernet. The KL5KUSB220 has been specifically designed to provide
a simple solution to communicate with Ethernet applications accomplished by its highly integrated
functionality. The USB controller consists of a central 16-bit processor, mask ROM, RAM buffer,
clock generator, Ethernet interface, UART, IRQ, Watchdog Timer, Serial interface, External and
Memory Interface. The SIE (Serial Interface Engine) is fully compatible with the USB2.0
specification. Our powerful internal processor enables Remote NDIS (Network Drive) which gives
compatibility with next generation operating systems and faster data transfer. This USB to
Ethernet controller is ideal for LAN (Local Area Network), HAN (Home Area Network), Cable
Modem, Set Top Boxes, or Mobile Networking applications.
Features
• Advanced 16 Bit processor for USB transaction
processing and control data processing
• 100Base-T compatibility
• USB interface version 2.0 compliant
• SIE (Serial Interface Engine)
• Internal Clock Generation - Utilizes low cost
external 12MHz crystal circuitry
• MII Physical Layer interface
• Remote NDIS for faster data transfer.
• Fully IEEE compliant 100 Mbit/sec
Ethernet MAC Layer. Interfaces serially of
an external ENDEC PHY.
• UART
• External memory interface
• 176 LQFP package
• Serial Interface for external EEPROM
• 32KB Internal RAM buffer
Block Diagram
Txd
Rxd UART
CK EEPROM
Serial Interface
DIO
2
INT 1-0
IRQ
MII PHY
Interface
100 Mb/s
Ethernet
Interface
Timer 0
Timer 1
RAM
(32KB)
Mask ROM
(16 KB)
16 Bit
Processor
Watchdog
Timer
SRAM Interface
16 Bit Address / Data Bus
Serial
Interface
Engine
Clock Gen. &
Internal PLL
UTMI Interface
A15-0
D15-0
Cntrl .
X1
X2
Ver. 1.0
Kawasaki LSI • 2570 North First Street • Suite 301 • San Jose, CA 95131 • Tel: (408) 570-0555 • Fax: (408) 570-0567 • www.klsi.com
1
1 page  
Pin #
LQFP
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
I/O
GND
GND
GND
VDD
N/C
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
VDD
VDD
IN
XIN
XOUT
GND
IN
OUT
VDD
IN
GND
IN
OUT
VDD
GND
GND
GND
VDD
N/C
OUT
OUT
IN
GND
GND
GND
VDD
N/C
IN
IN
IN
OUT
I/O
I/O
VDD
N/C
GND
Pin Name
GND
GND
GND
VDD
N/C
ERXD[0]
ERXD[1]
ERXD[2]
ERXD[3]
ECOL
ETXD[0]
ETXD[1]
ETXD[2]
ETXD[3]
VDD
VDD
PLLEN1
CLK
X2
GND
VCO_IN1
CP_OUT1
VDD
PLLEN2
GND
VCO_IN2
CP_OUT2
VDD
GND
GND
GND
VDD
N/C
ETXER
ETXEN
ERXER
GND
GND
GND
VDD
N/C
ERXDV
n_TST
n_RESET
X_PCLK
IO[0]
IO[1]
VDD
N/C
GND
KL5KUSB220
USB2.0 to 100 Ethernet Controller
Description
MII receive data 0.
MII receive data 1.
MII receive data 2.
MII receive data 3.
MII collision detected.
MII transmit data 0.
MII transmit data 1.
MII transmit data 2.
MII transmit data 3.
PLL #1 enable.
12 MHz clock/crystal input.
12 MHz crystal output.
PLL #1 VCO IN.
PLL #1 VCO OUT.
PLL #2 enable.
PLL #2 VCO IN.
PLL #2 VCO OUT.
MII transmit error.
MII transmit enable to PHY.
MII receive error.
MII receive data valid.
Test pin.
Reset.
Processor clock.
GPIO 0
GPIO 1
Ver. 1.0
Kawasaki LSI • 2570 North First Street • Suite 301 • San Jose, CA 95131 • Tel: (408) 570-0555 • Fax: (408) 570-0567 • www.klsi.com
5
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet KL5KUSB220.PDF ] | |
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