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PDF KL5KUSB121 Data sheet ( Hoja de datos )
| Número de pieza | KL5KUSB121 | |
| Descripción | USB to 10/100 Ethernet Controller | |
| Fabricantes | Kawasaki | |
| Logotipo |  |
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PRELIMINARY
KL5KUSB121
General Description
USB to 10/100 Ethernet Controller
The Kawasaki KL5KUSB121 Controller is a unique single chip solution to interface peripheral
devices to the Universal Serial Bus (USB) and Ethernet. The KL5KUSB121 has been specifically
designed to provide a simple solution to communicate with Ethernet applications as well as other
USB peripheral devices. This has been accomplished by its highly integrated functionality. The
USB controller consists of a central 16-bit processor, mask ROM, RAM buffer, clock generator,
Ethernet interface, UART, IRQ, Watchdog Timer, Serial interface, External Memory Interface and
SPORT Interface. The SIE (Serial Interface Engine) is fully compatible with the USB specification.
Our powerful internal processor enables Remote NDIS (Network Drive) which gives compatibility
with next generation operating systems and faster data transfer. This USB to Ethernet controller
is ideal for LAN (Local Area Network), HAN (Home Area Network), Cable Modem, Set Top
Boxes, or Mobile Networking applications.
Features
• Advanced 16 Bit processor for USB transaction
processing and control data processing
• 10/100Base-T compatibility
• USB interface ver. 1.0/1.1 compliant
• Transceivers and SIE (Serial Interface Engine)
• Internal Clock Generation - Utilizes low cost
external 12MHz crystal circuitry
• MII Physical Layer interface
• Remote NDIS for faster data transfer.
• Fully IEEE 802.3 compliant 10 Mbit/sec
Ethernet MAC Layer. Interfaces serially of
an external ENDEC PHY.
• UART
• External memory interface
• LQFP package
• Serial Interface for external EEPROM
• 1.5K x 16 Internal RAM buffer
Block Diagram
Txd
Rxd UART
CK EEPROM
Serial Interface
DIO
2
INT 1-0
IRQ
MII PHY
Interface
10/100 Mb/s
Ethernet
Interface
Timer 0
Timer 1
RAM
(3KB)
Mask ROM
(8KB)
16 Bit
Processor
Watchdog
Timer
SRAM Interface
16 Bit Address / Data Bus
Serial
Interface
Engine
Clock Gen. &
Internal PLL
USB Interface
Data -
Data +
A15-0
D15-0
Cntrl .
X1
X2
Ver. 1.1
Kawasaki LSI • 2570 North First Street • Suite 301 • San Jose, CA 95131 • Tel: (408) 570-0555 • Fax: (408) 570-0567 • www.klsi.com
1
1 page  
Pin #
LQFP
98
99
100
I/O
IN/OUT
IN/OUT
IN
PRELIMINARY
KL5KUSB121
Pin Name
USB to 10/100 Ethernet Controller
Description
XD_14
XD_15
VDD
External Data Pins
External Data Pins
VDD
Function Description
16 Bit Processor
The integrated 16 bit processor serves as a micro controller for USB peripherals. The
processor can execute approximately five million instructions per second. With this
processing power it allows the design of intelligent peripherals that can process data prior
to passing it on to the host PC, thus improving overall performance of the system. The
masked ROM (4K X 16) in the KL5KUSB121 or external memory contains a specialized
instruction set that has been designed for highly efficient coding of processing algorithms
and USB transaction processing.
The 16-bit processor is designed for efficient data execution by having direct access to
the RAM Buffer, external memory, I/O interfaces, and all the control and status registers.
The divide/multiply feature expands the capability of USB peripherals.
The processor supports prioritized vectored hardware interrupts. In addition, as many as
240 software interrupt vectors are available.
The processor provides six addressing modes, supporting memory-to-memory, memory-
to-register, register-to-register, immediate-to-register or immediate-to-memory
operations. Register, direct, immediate, indirect, and indirect indexed addressing modes
are supported. In addition, there is an auto-increment mode in which a register, used as
an address pointer is automatically incremented after each use, making repetitive
operations more efficient both from a programming and a performance standpoint.
The processor features a full set of program control, logical, and integer arithmetic
instructions. All instructions are sixteen bits wide, although some instructions require
operands, which may occupy another one or two words. Several special “ short
immediate” instructions are available, so that certain frequently used operations with
small constant operand will fit into a 16-bit instruction.
RAM Buffer
The USB controller contains a 3K byte (1.5K X 16) internal buffer memory. The memory
is used to buffer data and USB packets and accessed by the 16 Bit processor and the
SIE. USB transactions are automatically routed to the memory buffer. The 16-bit
processor has the ability to set up pointers and block sizes in buffer memory for USB
transactions. Data is read from the interface and is processed and packetized by the 16-
bit I/O processor.
Ver. 1.1
Kawasaki LSI • 2570 North First Street • Suite 301 • San Jose, CA 95131 • Tel: (408) 570-0555 • Fax: (408) 570-0567 • www.klsi.com
5
5 Page 
PRELIMINARY
KL5KUSB121
USB to 10/100 Ethernet Controller
Table 3.1.2 PHY SQE Transmit AC Characteristics (over recommended range)
Symbol
Parameter
Min Typ Max Unit Not
e
Tcol PHYCOL assert delay – – 1.6 us –
from PHYTEN fall
Tpco PHYCOL low width
0.5 –
– us –
3.2 U2E to PHY receive
Figure 3.2.1 U2E from PHY Receive AC Timing
PHYRCLK
(IN)
Trck
Tscd
Trch
Trcl
Thcd
PHYCD
(IN)
PHYRXD
(IN)
Tsrd
first
Thrd
last
Table 3.2.1 Receive from PHY AC Characteristics (over recommended range)
Symbol
Parameter
Min Typ Max Unit Not
e
Trck PHYRCLK period
– 100 – ns 1
Frck PHYRCLK frequency – 10 – MH 1
z
Trch PHYRCLK high width – 50 – ns –
Trcl PHYRCLK low width – 50 – ns –
Tscd PHYCD setup time
to PHYRCLK rise
20 –
– ns –
Thcd PHYCD hold time
from PHYTCLK rise
10 –
– ns –
Tsrd
PHYRXD setup time
to PHYRCLK fall
20 –
– ns –
Thrd
PHYRXD hold time
from PHYRCLK fall
10 –
– ns –
Note: 1) PHY generates the 10MHz clock.
Ver. 1.1
Kawasaki LSI • 2570 North First Street • Suite 301 • San Jose, CA 95131 • Tel: (408) 570-0555 • Fax: (408) 570-0567 • www.klsi.com
11
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet KL5KUSB121.PDF ] | |
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