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QR0001 반도체 회로 부품 판매점

QuickRing Data Stream Controller



National Semiconductor 로고
National Semiconductor
QR0001 데이터시트, 핀배열, 회로
www.DataSheet4U.com
PRELIMINARY
October 1994
QR0001
QuickRingTM Data Stream Controller
General Description
QuickRing is a point-to-point data transfer architecture de-
signed to facilitate high speed data streams The QuickRing
architecture can be applied both inside the chassis as well
as outside the chassis environments to increase data
throughput Each QR0001 QuickRing Controller node in the
ring is capable of streaming up to 231 MSamples s per sig-
nal line simultaneously including protocol overhead This
device is intended for use in applications that handle high-
bandwidth data streams associated with graphics uncom-
pressed video disk arrays high-speed local area networks
multiprocessor systems and to interconnect peripherals
over a few meters of cable The QR0001 QuickRing Con-
troller can be used to augment the performance of tradition-
al backplane buses in personal computers workstations
and high-end systems The QR0001 is useful for routing
high-bandwidth streams in systems that are larger or topo-
logically more complex than bus-based systems
Features
Y 160-pin PQFP package
Y 16 node single ring capability
Y Peak theoretical rate over 1 GByte sec for 16 node
ring
Y Support for Multi-Ring topologies
Y Error detection detects 1- and 2-bit errors
RING INTERFACE
Y Precision PLL captures data at 231 MSamples s max
Y 33 MHz maximum ring clock frequency
Y Low Voltage Differential Signaling (LVDS) ring interface
(IEEE P1596 3)
CLIENT INTERFACE
Y 132 MBytes s data transfer rate at both Tx and Rx
ports
Y 32-bit transmit and receive data ports
Y Readable internal diagnostic register
Y TTL signal interface
Block Diagram
QuickRingTM is a trademark of Apple Computer Incorporated
C1995 National Semiconductor Corporation TL F 11928
TL F 11928 – 1
RRD-B30M75 Printed in U S A


QR0001 데이터시트, 핀배열, 회로
Table of Contents
1 0 SIGNAL DESCRIPTION
2 0 BASIC STRUCTURE
3 0 CLIENT INTERFACE
3 1 Type and Symbol Fields at the Client Ports
3 2 Client Transmit Port
3 3 Transmit Port Timing Relationships
3 4 Client Receive Port
3 5 Receive Port Timing Relationships
3 5 1 Client Receive Port Interface
Recommendations (PIPE asserted)
3 6 Client Interface Field Definitions
3 7 Client Type Fields
3 8 Transmit Port Head Fields
3 9 Receive Port Head Fields
3 10 Payload Symbols at the Rx and Tx Ports
3 11 Null Symbols at the Rx and Tx Ports
3 12 The HOP fields and the Uniqueness of
Symbol Streams
3 13 Summary of Client Port Field Format
3 14 Readable Registers
3 15 Error Detection
4 0 RING INTERFACE
4 1 Type and Symbol Field at the Ring Ports
4 2 Data and Frames
4 3 Symbol Flux on Ring
4 4 Data on the Ring (Head Payload Tail)
4 5 Access on the Ring
(Voucher Ticket Abort Null)
4 6 Mapping of Type Frame Data and EDC Code
on the Ring
4 7 Ring Interface Field Definitions
4 8 Routing Symbols are Common to All Ports
4 9 Ring Type Fields
4 10 Head Symbol on the Ring
4 11 Payload Symbols on the Ring
4 12 Tail Symbol on the Ring
4 13 Access Symbols on the Ring
4 14 Summary of Ring Port Field Format
5 0 CLOCK SIGNALS
6 0 ABORT SIGNAL
7 0 BRIDGES
8 0 LITTLE BIG ENDIAN ISSUES
9 0 RESET AND INITIALLZATION
9 1 Reset
9 2 Node 0 Selection and Initialization
9 3 Node ID Assignment
9 4 Sequence for Node 0
9 5 Sequence for All Qther Nodes on Ring
10 0 QR0001 OPERATION FLOW
10 1 Ring Traffic Flow Priorities for DnSS port
Transmissions
10 2 Inside the Source Node (Device Transmitting Data)
10 3 Summary of Source Node Actions
10 4 Inside the Target Node
10 5 Summary of Target Node Actions
11 0 BOARD CONSIDERATIONS
11 1 Upstream Port Signal Termination
11 2 QuickRing Physical Layer Details
12 0 POWER AND DECOUPLING ISSUES
12 1 Power Issues
12 2 Decoupling Issues
13 0 DC ELECTRICAL CHARACTERISTICS
14 0 AC TIMING PARAMETERS
15 0 CONNECTION DIAGRAM
16 0 GLOSSARY
17 0 REVISION NOTES
2




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QR0001 controller

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