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PDF W78E051B Data sheet ( Hoja de datos )
| Número de pieza | W78E051B | |
| Descripción | 8-Bit Microcontroller | |
| Fabricantes | Winbond Electronics | |
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W78E51B Data Sheet
8-BIT MICROCONTROLLER
Table of Contents-
1. GENERAL DESCRIPTION ......................................................................................................... 3
2. FEATURES ................................................................................................................................. 3
3. PIN CONFIGURATIONS ............................................................................................................ 4
4. PIN DESCRIPTION..................................................................................................................... 5
5. BLOCK DIAGRAM ...................................................................................................................... 6
6. FUNCTIONAL DESCRIPTION ................................................................................................... 7
6.1 New Defined Peripheral.................................................................................................. 7
6.2 Reduce EMI Emission .................................................................................................... 8
6.3 Watchdog Timer ............................................................................................................. 9
6.4 Clock ............................................................................................................................. 10
6.5 Power Management...................................................................................................... 10
6.6 Reset............................................................................................................................. 11
6.7 On-Chip ROM Characteristics ...................................................................................... 11
6.7.1 Read Operation ..............................................................................................................11
6.7.2 Output Disable ConditDioant.a..S...h..e..e..t..4..U....c..o..m........................................................................11
6.7.3 Program Operation .........................................................................................................11
6.7.4 Program Verify Operation ...............................................................................................11
6.7.5 Erase Operation .............................................................................................................11
6.7.6 Erase Verify Operation ...................................................................................................11
6.7.7 Program/Erase Inhibit Operation ....................................................................................12
7. SECURITY BITS ....................................................................................................................... 12
7.1 Lock Bit ......................................................................................................................... 13
7.2 MOVC Inhibit................................................................................................................. 13
7.3 Encryption ..................................................................................................................... 13
8. ELECREICAL CHARACTERISTICS......................................................................................... 14
8.1 Absolute Maximum Ratings .......................................................................................... 14
8.2 D.C. Characteristics...................................................................................................... 14
8.3 A.C. Characteristics ...................................................................................................... 15
8.3.1 Clock Input Waveform ....................................................................................................16
8.3.2 Program Fetch Cycle......................................................................................................16
8.3.3 Data Read Cycle ............................................................................................................16
8.3.4 Data Write Cycle.............................................................................................................17
8.3.5 Port Access Cycle ..........................................................................................................17
8.3.6 Program Operation .........................................................................................................17
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4. PIN DESCRIPTION
SYMBOL
EA
DESCRIPTIONS
EXTERNAL ACCESS ENABLE: This pin forces the processor to execute out of
external ROM. It should be kept high to access internal ROM. The ROM address and
data will not be presented on the bus if EA pin is high and the program counter is within
on-chip ROM area.
PSEN
PROGRAM STORE ENABLE: PSEN enables the external ROM data onto the Port 0
address/ data bus during fetch and MOVC operations. When internal ROM access is
performed, no PSEN strobe signal outputs from this pin.
ALE
ADDRESS LATCH ENABLE: ALE is used to enable the address latch that separates
the address from the data on Port 0.
RST
RESET: A high on this pin for two machine cycles while the oscillator is running resets
the device.
XTAL1
CRYSTAL1: This is the crystal oscillator input. This pin may be driven by an external
clock.
XTAL2 CRYSTAL2: This is the crystal oscillator output. It is the inversion of XTAL1.
VSS GROUND: Ground potential
VDD POWER SUPPLY: Supply voltage for operation.
P0.0−P0.7
PORT 0: Port 0 is
address/data bus
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drain and should connect to pull up resistors if necessary while in programming.
PORT 1: Port 1 is a bi-directional I/O port with internal pull-ups. The bits have alternate
functions which are described below:
P1.0−P1.7 T2(P1.0): Timer/Counter 2 external count input
T2EX(P1.1): Timer/Counter 2 Reload/Capture control
P2.0−P2.7
PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also provides
the upper address bits for accesses to external memory.
PORT 3: Port 3 is a bi-directional I/O port with internal pull-ups. All bits have alternate
functions, which are described below:
RXD(P3.0) : Serial Port receiver input
TXD(P3.1) : Serial Port transmitter output
INT0 (P3.2) : External Interrupt 0
P3.0−P3.7 INT1(P3.3) : External Interrupt 1
T0(P3.4) : Timer 0 External Input
T1(P3.5) : Timer 1 External Input
WR (P3.6) : External Data Memory Write Strobe
RD (P3.7) : External Data Memory Read Strobe
PORT 4: Another bit-addressable bidirectional I/O port P4. P4.3 and P4.2 are alternative
P4.0−P4.3 function pins. It can be used as general I/O port or external interrupt input sources
(INT2 /INT3 ).
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6.6 Reset
The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two
machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to
deglitch the reset line when the W78E51B is used with an external RC network. The reset logic also
has a special glitch removal circuit that ignores glitches on the reset line.
During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit
4) to 00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset.
6.7 On-Chip ROM Characteristics
The W78E51B has several modes to program the on-chip Flash EPROM. All these operations are
configured by the pins RST, ALE, PSEN , A9CTRL(P3.0), A13CTRL(P3.1), A14CTRL(P3.2),
OECTRL(P3.3), CE (P3.6), OE (P3.7), A0(P1.0) and VPP( EA ). Moreover, the A15−A0(P2.7−P2.0,
P1.7−P1.0) and the D7−D0(P0.7−P0.0) serve as the address and data bus respectively for these
operations.
6.7.1 Read Operation
This operation is supported for customer to read their code and the Security bits. The data will not be
valid if the Lock bit is programmed to low.
6.7.2 Output Disable Condition
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When the OE is set to high, no data output appears on the D7..D0.
6.7.3 Program Operation
This operation is used to program the data to ROM and the security bits. Program operation is done
when the VPP is reach to VCP (12.5V) level, CE set to low, and OE set to high.
6.7.4 Program Verify Operation
All the programming data must be checked after program operations. This operation should be
performed after each byte is programmed; it will ensure a substantial program margin.
6.7.5 Erase Operation
An erase operation is the only way to change data from 0 to 1. This operation will erase all the ROM
cells and the security bits from 0 to 1. This erase operation is done when the VPP is reach to VEP level,
CE set to low, and OE set to high.
6.7.6 Erase Verify Operation
After an erase operation, all of the bytes in the chip must be verified to check whether they have been
successfully erased to 1 or not. The erase verify operation automatically ensures a substantial erase
margin. This operation will be done after the erase operation if VPP = VEP (14.5V), CE is high and
OE is low.
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