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OZ962
High-Efficiency Inverter Controller
FEATURES
• Single-stage power conversion, input voltage
range of 5V to 18V
• Reduces the number of components and board
size by 30% compared with conventional design
• Supports both floating and grounded secondary
designs
• 90% efficiency vs. typical 75% efficiency of
conventional designs
• Internal open-lamp and short-circuit protections
• Wide dimming range
• Supports synchronization among multiple
inverter modules
• Reliable 2 -winding transformer design,
eliminates arcing problems
• Constant frequency, symmetrical, sinusoidal
drive
ORDERING INFORMATION
OZ962R - 16 lead TSSOP
OZ962G - 16-pin plastic SOP
GENERAL DESCRIPTION
The OZ962 is a unique high-efficiency, CCFL
backlight controller. It generates symmetrical,
near sinusoidal output voltage and current
waveforms for driving a CCFL backlight. The
OZ962 operates in a single, constant frequency,
pulse-width-modulation (PWM) mode. Typical
operating frequency ranges between 30 KHz to
100 KHz, depending on the CCFL and the
transformer’s characteristics.
Operating in a PWM push-pull manner, the
transformer in the OZ962 backlight inverter
requires only one primary winding and one
secondary winding, with the secondary winding
requiring no fold-back treatment.
The OZ962 is available in both 16-pin SOIC and
TSSOP packages. It is specified over the
commercial temperature range: 0 oC to +70 oC.
TYPICAL APPLICATION CIRCUIT
F1
VDD (+12V) 1A Fast Fuse
ENA
GND
CN1
R2
10K
R3
5.1K
+ C1
- 22u
25V
R1 R9
220K 200K C9
.01u
C2 C3
0.1u
330p
1
REF
U1
16
VDD
2 OZ962G 15
OVP
RT
3
NC
14
CT
4
SCP
13
CLK
5
ADJ
12
ENA
6
FB
11
NDR
7
CMP
10
PDR
8
GND
9
SST
R11 R4
1M 15K
R5
10K
C5
220p
C4
0.1u
R10
100
C8
0.22u
R7
100K
R6
30
3 U2
Q2 *
33T
4 C6 2.2u
5,6 50V
SI4559EY
-+
7,8
2
Q1
1
R8
0.5
R12
750
C7
* 68p
2200T 3KV
3.5W
R14
1.0K
R13
100
Figure 1. Typical Floating Secondary Application
Circuit
03/01/00
©Copyright 1999 by O2Micro
OZ962-SF -2.7
All Rights Reserved
Page 1
U.S. Patent #5,619,402
OZ962
FUNCTIONAL BLOCK DIAGRAM
Ct(14) Rt(15)
OVP(2)
VDD(16)
Under Voltage
Lockout
REF(1)
Band Gap
Reference
ADJ(5)
FB(6)
CMP(7)
40k
OSC
RAMP
Error
Amp.
Vcmp
3V
Vdd
OVP Voltage
Generator
OVP
OVP=Vref-(Vdd - 1)(12.5/150)
D=1.1(OVP)/2.5 - 0.2
Break
Before
Make
N-Clamp
Vref (2.5V)
RAMP
OSC
S
Q
RQ
Ve
Ve=Vcmp-2*(Vcmp-SST-Vgs)
P-Clamp
1/2F
60k
30k
1k SST
Dmax
Clamp
9k OVP
NDR(11)
PDR(10)
CLK(13)
SST(9)
3µ A
10µA
2.0v
SST
2µA
SCP(4)
Note :
OVP – Over Voltage Protection
SCP – Short-Circuit Protection
UVL – Under Voltage Lockout
OVP
SCP & OVP inhibited during
start-up
ADJ
OVP
SCP
UVL
shut
down
latch
Figure 2. Functional Block Diagram
ENA(12)
GND(8)
OZ962-SF -2.7
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