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VIC068A-AC 반도체 회로 부품 판매점

VMEbus Interface Controller



Cypress Semiconductor 로고
Cypress Semiconductor
VIC068A-AC 데이터시트, 핀배열, 회로
VIC068A
Features
• Complete VMEbus interface controller and arbiter
— 58 internal registers provide configuration control
and status of VMEbus and local operations
— Drives arbitration, interrupt, address modifier utility,
strobe, address lines A07 through A01 and data lines
D07 through D00 directly, and provides signals for
control logic to drive remaining address and data
lines
— Direct connection to 68xxx family and mappable to
non-68xxx processors
Complete master/slave capability
— Supports read, write, write posting, and block trans-
fers
— Accommodates VMEbus timing requirements with
internal digital delay line (12-clock granularity)
— Programmable metastability delay
— Programmable data acquisition delays
— Provides timeout timers for local bus and VMEbus
transactions
Interleaved block transfers over VMEbus
— Acts as DMA master on local bus
— Programmable burst count, transfer length, and in-
terleaved period interval
— Supports local module-based DMA
Arbitration support
— Supports single-level, priority and round robin arbi-
tration
— Supports fair request option as requester
Interrupt support
— Complete support for the VMEbus interrupts: inter-
rupter and interrupt handler
VMEbus Interface Controller
— Seven local interrupt lines
— 8-level interrupt priority encode
— Total of 29 interrupts mapped through the VIC068A
Miscellaneous features
— Refresh option for local DRAM
— Four broadcast location monitors
— Four module-specific location monitors
— Eight interprocessor communications registers
— PGA or QFP packages
— Compatible with IEEE Specification 1014, Rev. C
— Supports RMC operations
See the VMEbus Interface Handbook for more informa-
tion
Functional Description
The VMEbus interface controller (VIC068A) is a single chip
designed to minimize the cost and board area requirements
and to maximize performance of the VMEbus interface of a
VMEbus master/slave module. This can be implemented on
VIC068A either an 8-bit, 16-bit, or 32-bit VMEbus system. The
VIC068A performs all VMEbus system controller functions
plus many others, which simplify the development of
VIC068Aa VMEbus interface. The VIC068A utilizes patented
on-chip output buffers. These CMOS high-drive buffers pro-
vide direct connection to the address and data lines. In addi-
tion to these signals, the VIC068A connects directly to the ar-
bitration, interrupt, address modifier, utility and strobe lines.
Signals are provided which control data direction and latch
functions needed for a 32-bit implementation.
The VIC068A was developed through the efforts of a consor-
tium of board vendors, under the auspices of the VMEbus In-
ternational Trade Association (VITA). The VIC068A thus in-
sures compatibility between boards designed by different
manufacturers.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
December 1990 - Revised July 23, 1997


VIC068A-AC 데이터시트, 핀배열, 회로
VIC068A
Pin Configurations
Pin Grid Array (PGA)
Bottom View
AB
CDE
FG
HJ
KL
MN
P
R
GND
IPL2* LIACKO* LIRQ2* LIRQ5*
ASIZ1 ASIZ0 SLSEL1* WORD* FIACK*
A02
A04
VCC
GND
IRQ4*
LD6
BLT*
IPL1*
VCC
LIRQ1* LIRQ4* LIRQ6* ICFSEL* MWB*
A01
A03
A05
A07 IRQ3* IRQ7*
LD2
LD5 DEDLK* IPL0*
LAEN
LIRQ3* LIRQ7*
GND SLSEL0*
GND
A06
IRQ1*
IRQ2*
IRQ6* ACFAIL*
LD1
LD3
LD7
LOCATOR
PIN
LA7 LD0 LD4
IRQ5*
VCC IACKOUT*
SYSFAIL* SYSRESET* DTACK*
LA3 LA5 LA6
IACKIN* IACK*
AM0
LA2 LA4 GND
LA1 LA0 VCC
GND AS* AM1
GND
AM2
AM3
CS* DSACK1* DS*
PAS*
LBERR* RESET*
DSACK0*
R/W*
FC1
VCC LWORD* AM4
BERR* WRITE* AM5
BR2*
DS1*
DS0*
HALT*
RMC*
LBR*
BBSY*
BR1*
BR0*
FC2
SIZ0
SCON* CLK64M
LADI
GND
VCC
GND
VCC
D00 BGOUT1* BGIN2* BGIN0* BR3*
GND
SIZ1
IRESET* LADO
LEDI
DDIR LWDENIN* DENO*
D06
D03 D01 GND BGOUT0* BGIN3* BGIN1* BCLR*
LBG*
ABEN*
VCC
LEDO UWDENIN* SWDEN* ISOBE*
D07
D05
D04 D02 BGOUT3* BGOUT2* SYSCLK GND
VIC068A–1
2




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