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PDF 74F1763 Data sheet ( Hoja de datos )
| Número de pieza | 74F1763 | |
| Descripción | Intelligent DRAM controller IDC | |
| Fabricantes | NXP Semiconductors | |
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INTEGRATED CIRCUITS
74F1763
Intelligent DRAM controller (IDC)
Product specification
Supersedes data of 1989 Nov 17
IC15 Data Handbook
1999 Jan 08
Philips
Semiconductors
1 page  
Philips Semiconductors
Intelligent DRAM controller (IDC)
Product specification
74F1763
FUNCTIONAL DESCRIPTION
The 74F1763 1 Megabit Intelligent DRAM Controller (IDC) is a
synchronous device with most signal timing being a function of the
CP input clock.
Arbitration
Once the DRAM’s RAS precharge time has been satisfied, the REQ
input is sampled on each rising edge of the CP clock and an
internally generated refresh request is sampled on each falling edge
of the same clock. When only one of these requests is sampled as
active the appropriate memory cycle will begin immediately. For a
memory access cycle this will be indicated by GNT and RAS outputs
both being asserted and for a refresh cycle by multiplexing refresh
address to the MA0–9 outputs and subsequent assertion of RAS
after 1/2CP clock cycle. If both memory access and refresh requests
are active at a given time the request sampled first will begin
immediately and the other request (if still asserted) will be serviced
upon completion of the current cycle and it’s associated RAS
precharge time.
Memory access
The row (RA0–9) and column (CA0–9) address inputs are latched
when ALE input is High. When ALE is Low the input addresses
propagate directly to the outputs. When GNT and RAS are asserted,
after a REQ has been sampled the RA0–9 address inputs will have
already propagated to the MA0–9 outputs for the row address. One
or one-half CP clock cycles later (depending on the state of the
HLDROW input) the column address (CA0–9) inputs are propagated
to the MA0–9 outputs. CAS is always asserted one and one-half CP
clock cycles after RAS is asserted. If the PAGE input is High, RAS
will be negated approximately four CP clock cycles after its initial
assertion. At this time the DTACK output becomes valid indicating
the completion of a memory access cycle. The IDC will maintain the
state of all its outputs until the REQ input is negated ( see timing
waveforms).
Row address hold times
If the HLDROW input of the IDC is High the row address outputs will
remain valid 1/2 CP clock cycle after RAS is asserted. If the
HLDROW input is Low the row address outputs will remain valid one
CP clock cycle after RAS is asserted.
RAS precharge timing
In order to meet the RAS precharge requirement of dynamic RAMs,
the controller will hold-off a subsequent RAS signal assertion due to
a processor access request or a refresh cycle for four or three full
CP clock cycles from the previous negation of RAS, depending on
the state of the PRECHRG input. If the PRECHRG input is Low,
RAS remains High for at least 4 CP clock cycles. If the PRECHRG
input is High RAS remains High for at least 3 CP clock cycles.
Refresh timing
The refresh address counter wakes-up in an all 1’s state and is an
up counter. The refresh clock (RCP) is internally divided down by 64
to produce an internal refresh request. This refresh request is
recognized either immediately or at the end of a running memory
access cycle. Due to the possibility that page mode access cycles
may be lengthy, the controller keeps track of how many refresh
requests have been missed by logging them internally (up to 128)
and servicing any pending refresh requests at the end of the
memory access cycle. The controller performs RAS-only refresh
cycles until all pending refresh requests are depleted.
Page-mode access
Fast accesses to consecutive locations of DRAM can be realized by
asserting the PAGE input as shown in the timing waveforms. In this
mode, the controller does not automatically negate RAS after four
CP clock cycles, but keeps it asserted throughout the access cycle.
By using external gates, the CAS output can be gated on and off
while changing the column address inputs to the controller, which
will propagate to the MA0–MA9 address outputs and provide a new
column address. This is only useful if the ALE input is Low, enabling
the user to charge addresses. This mode can be used with DRAMs
that support page or nibble mode addressing.
Output driving characteristics
Considering the transmission line characteristic of the DRAM arrays,
the outputs of the IDC have been designed to provide incident-edge
switching (in Dual-Inline-Packaged memory arrays), needed in high
performance systems. For more information on the driving
characteristics, please refer to Philips Semiconductors application
note AN218. The driving characteristics of the 74F1763 are the
same as those of the 74F765 shown in the application note.
1999 Jan 08
5
5 Page 
Philips Semiconductors
Intelligent DRAM controller (IDC)
Product specification
74F1763
TIMING DIAGRAMS (Continued)
CP
REQ
GNT
8
7
10
9
11
ALE
12
RA0–9,
CA0–9
ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ1VA3ÇÇADLDIDREÇÇ1S4S ÇÇÇÇÇÇÇÇÇÇÇÇNOÇÇTE1 ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ
15 HLDROW = 0
16 HLDROW = 1
MA0–9
REFRESH
ADDRESS
REFRESH
ADDRESS
NOTE 2 VALID ROW ADDRESS
VALID COLUMN ADDRESS
PRECHRG = 0 PRECHRG = 1
RAS
18
17
19
21 22
20
36
35
23
25
PAGE = 1
24
26
CAS
PAGE
DTACK
3-STATE
28
ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ27ÇÇÇNOTEÇÇÇ3 ÇÇÇÇÇÇ 29
30 31
32
3-STATE
NOTE 1: If the RA0–9 and CA0–9 address inputs are not latched, RA0–9 inputs should remain valid until row address hold time is met and CA0–9 inputs should remain valid until column
address hold time is met.
NOTE 2: MA0–9 outputs will contain the present row address on the RA0–RA9 inputs or the last row address latched into the device.
NOTE 3: PAGE input may be asserted anytime before this rising clock edge in order to hold RAS low.
SF01406
Figure 4. Memory access cycle timing following a refresh cycle
1999 Jan 08
11
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| PDF Descargar | [ Datasheet 74F1763.PDF ] | |
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