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FN4871 반도체 회로 부품 판매점

Multiple Linear Power Controller with ACPI Control Interface



Intersil Corporation 로고
Intersil Corporation
FN4871 데이터시트, 핀배열, 회로
TM
Data Sheet
HIP6502B
May 2000
File Number 4871
Multiple Linear Power Controller with
ACPI Control Interface
The HIP6502B complements either an HIP6020 or an
HIP6021 in ACPI-compliant designs for microprocessor and
computer applications. The IC integrates four linear
controllers/regulators, switching, monitoring and control
functions into a 20-pin SOIC package. One linear controller
generates the 3.3VDUAL/3.3VSB voltage plane from the ATX
supply’s 5VSB output, powering the south bridge and the
PCI slots through an external pass transistor during sleep
states (S3, S4/S5). A second transistor is used to switch in
the ATX 3.3V output for operation during S0 and S1/S2
(active) operating states. Two linear controllers/regulators
supply at choice either or both of the computer system’s
2.5V or 3.3V memory power through external pass
transistors in active states. During sleep states, integrated
pass transistors supply the sleep power. Another controller
powers up the 5VDUAL plane by switching in the ATX 5V
output in active states, and the ATX 5VSB in sleep states.
One internal regulator outputs a dedicated, noise-free 2.5V
clock chip supply. The HIP6502B’s operating mode (active
outputs or sleep outputs) is selectable through two digital
control pins, S3 and S5. Enabling sleep state support on the
5VDUAL output is offered through the EN5VDL pin. In active
state, the 3.3VDUAL and 3.3VMEM linear regulators use
external N-channel pass MOSFETs to connect the outputs
directly to the 3.3V input supplied by an ATX (or equivalent)
power supply, for minimal losses. In sleep state, power
delivery on both outputs is transferred to NPN transistors -
external to the controller on the 3.3VDUAL, internal on the
3.3VMEM. Active state regulation on the 2.5VMEM output is
performed through an external NPN transistor. In sleep
state, conduction on this output is transferred to an internal
pass transistor. The 5VDUAL output is powered through two
external MOS transistors. In sleep states, a PMOS (or PNP)
transistor conducts the current from the ATX 5VSB output;
while in active state, current flow is transferred to an NMOS
transistor connected to the ATX 5V output. The operation of
the 5VDUAL output is dictated not only by the status of the
S3 and S5 pins, but that of the EN5VDL pin as well. The
3.3VDUAL/3.3VSB output is active for as long as the ATX
5VSB voltage is applied to the chip. The 2.5VCLK output is
only active during S0 and S1/S2, and uses the 3V3 pin as
input source for its internal pass element.
Ordering Information
TEMP.
PART NUMBER RANGE (oC)
PACKAGE
HIP6502BCB
0 to 70 20 Ld SOIC
HIP6502BEVAL1 Evaluation Board
PKG.
NO.
M20.3
Features
• Provides 5 ACPI-Controlled Voltages
- 5VDUAL USB/Keyboard/Mouse (Active/Sleep)
- 3.3VDUAL/3.3VSB PCI/Auxiliary/LAN (Active/Sleep)
- 2.5VMEM RDRAM (Active/Sleep)
- 3.3VMEM SDRAM (Active/Sleep)
- 2.5VCLK Clock/Processor Terminations (Active Only)
• Excellent Output Voltage Regulation
- 3.3VDUAL/3.3VSB Output: ±2.0% Over Temperature;
Sleep State Only
- 2.5VMEM and 3.3VMEM Output: ±2.0% Over
Temperature; Both Operational States (3.3VMEM in
Sleep Only)
- 2.5VCLK Output: ±2.0% Over Temperature
• Small Size
- Very Low External Component Count
• Dual Memory Voltage Support Via MSEL Pin
- 2.5V for RDRAM Memory
- 3.3V for SDRAM Memory
- Both 2.5V and 3.3V for Flexible Systems
• Under-Voltage Monitoring of All Outputs with Centralized
FAULT Reporting and Temperature Shutdown
Applications
Motherboard Power Regulation for ACPI-Compliant
Computers
Pinout
HIP6502B
(SOIC)
TOP VIEW
VSEN2 1
5VSB 2
VSEN1 3
3V3DLSB 4
3V3DL 5
VCLK 6
3V3 7
EN5VDL 8
S3 9
S5 10
20 MSEL
19 DRV2
18 5V
17 12V
16 SS
15 5VDL
14 5VDLSB
13 DLA
12 FAULT
11 GND
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000


FN4871 데이터시트, 핀배열, 회로
Block Diagram
12V 3V3DLSB
12V MONITOR
10.8V/9.8V
EA4
TO 5VSB
VSEN1
EA3 +
-
TO UV
DETECTOR
FAULT
UV DETECTOR
3V3DL 5V
3V3 5VSB 5VDLSB DLA
5V MONITOR
4.5V/4.25V
5VSB POR
4.4V/3.2V
TEMPERATURE
MONITOR
(TMON)
3V3 MONITOR
2.97V/2.8V
MONITOR AND CONTROL
TO
UV DETECTOR
+ EA3
-
TO 3V3
+
1.265V
-
TO 5V
5VDL
10µA
+
3.75V
-
UV COMPARATOR
GND
SS
S3 S5 EN5VDL
TO UV
DETECTOR
EA2
-
+
MSEL
FIGURE 1.
VCLK
DRV2
VSEN2




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FN4871 controller

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FN4871

Multiple Linear Power Controller with ACPI Control Interface - Intersil Corporation