PDF FDC37N869TQFP Data sheet ( Hoja de datos )

Número de pieza	FDC37N869TQFP
Descripción	5V and 3.3V Super I/O Controller with Infrared Support for Portable Applications
Fabricantes	ETC
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FDC37N869 5V and 3.3V Super I/O Controller with Infrared Support for Portable Applications FEATURES § PC 99 Compliant § 5 Volt and 3.3 Volt Operation § Intelligent Auto Power Management § 16 Bit Address Qualification § 2.88MB Super I/O Floppy Disk Controller - Licensed CMOS 765B Floppy Disk Controller - Software and Register Compatible with SMSC’s Proprietary 82077AA Compatible Core - Supports One Floppy Drive Directly - Configurable Open Drain/Push-Pull Output Drivers - Supports Vertical Recording Format - 16 Byte Data FIFO - 100% IBM Compatibility - Detects All Overrun and Underrun Conditions - Sophisticated Power Control Circuitry (PCC) Including Multiple Power-Down Modes for Reduced Power Consumption - DMA Enable Logic - Data Rate and Drive Control Registers - Swap Drives A and B - Non-Burst Mode DMA Option - 48 Base I/O Address, 15 IRQ and 4 DMA Options - Forceable Write Protect and Disk Change Controls § Floppy Disk Available on Parallel Port Pins ACPI Compliant § Enhanced Digital Data Separator - 2Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250 Kbps Data Rates - Programmable Precompensation Modes § Serial Ports - Two High Speed NS16C550 Compatible UARTs with Send/Receive 16 Byte FIFOs - Supports 230k and 460k Baud - Programmable Baud Rate Generator - Modem Control Circuitry § Infrared Communications Controller - IrDA v1.1 (4Mbps), HPSIR, ASKIR, Consumer IR Support - 2 IR Ports - 96 Base I/O Address, 15 IRQ Options and 4 DMA Options § Multi-Mode Parallel Port with ChiProtect - Standard Mode - IBM PC/XT, PC/AT, and PS/2 Compatible Bi- directional Parallel Port - Enhanced Parallel Port (EPP) Compatible - EPP 1.7 and EPP 1.9 (IEEE 1284 Compliant) - Enhanced Capabilities Port (ECP) Compatible (IEEE 1284 Compliant) - Incorporates ChiProtect Circuitry for Protection Against Damage Due to Printer Power-On - 192 Base I/O Address, 15 IRQ and 4 DMA Options § Game Port Select Logic - 48 Base I/O Addresses § General Purpose Address Decoder - 16-Byte Block Decode SMSC DS – FDC37N869 ORDERING INFORMATION Order Number: FDC37N869TQFP 100 Pin TQFP Package 11/09/2000 1 page Configure.................................................................................................................................. 54 Version ..................................................................................................................................... 55 Relative Seek ............................................................................................................................. 55 Perpendicular Mode.................................................................................................................. 56 LOCK........................................................................................................................................ 57 ENHANCED DUMPREG ............................................................................................................. 57 COMPATIBILITY ............................................................................................................................ 57 PARALLEL PORT FLOPPY DISK CONTROLLER.......................................................................................... 57 SERIAL PORT (UART) ...................................................................................................................... 59 REGISTER DESCRIPTION...................................................................................................................... 59 RECEIVE BUFFER REGISTER (RB)............................................................................................ 59 TRANSMIT BUFFER REGISTER (TB) ......................................................................................... 59 INTERRUPT ENABLE REGISTER (IER)....................................................................................... 59 INTERRUPT IDENTIFICATION REGISTER (IIR) ............................................................................ 60 FIFO CONTROL REGISTER (FCR).............................................................................................. 62 LINE CONTROL REGISTER (LCR).............................................................................................. 63 MODEM CONTROL REGISTER (MCR) ....................................................................................... 64 LINE STATUS REGISTER (LSR) ................................................................................................ 65 MODEM STATUS REGISTER (MSR).......................................................................................... 66 SCRATCHPAD REGISTER (SCR) ............................................................................................... 67 PROGRAMMABLE BAUD RATE GENERATOR DIVISOR LATCHES ........................................... 67 The Affects of RESET on the UART Registers............................................................................ 68 FIFO INTERRUPT MODE OPERATION...................................................................................................... 68 FIFO POLLED MODE OPERATION......................................................................................................... 69 NOTES ON SERIAL PORT FIFO MODE OPERATION................................................................................... 70 GENERAL................................................................................................................................. 70 TX AND RX FIFO OPERATION................................................................................................... 71 INFRARED INTERFACE .................................................................................................................... 71 IRDA SIR/FIR AND ASKIR ................................................................................................................ 71 CONSUMER IR.................................................................................................................................. 72 HARDWARE INTERFACE...................................................................................................................... 72 IR HALF DUPLEX TURNAROUND DELAY TIME........................................................................................... 72 PARALLEL PORT............................................................................................................................. 74 IBM XT/AT COMPATIBLE, BI-DIRECTIONAL AND EPP MODES........................................................ 75 DATA PORT.............................................................................................................................. 75 STATUS PORT.......................................................................................................................... 75 CONTROL PORT ....................................................................................................................... 76 EPP ADDRESS PORT................................................................................................................ 77 EPP DATA PORT 0.................................................................................................................... 77 EPP DATA PORT 1.................................................................................................................... 77 EPP DATA PORT 2.................................................................................................................... 77 EPP DATA PORT 3.................................................................................................................... 77 EPP 1.9 OPERATION .................................................................................................................... 77 Software Constraints................................................................................................................. 78 EPP 1.9 Write............................................................................................................................ 78 EPP 1.9 Read ............................................................................................................................ 78 EPP 1.7 OPERATION .................................................................................................................... 79 Software Constraints................................................................................................................. 79 EPP 1.7 Write............................................................................................................................ 79 EPP 1.7 Read ............................................................................................................................ 79 EXTENDED CAPABILITIES PARALLEL PORT.................................................................................. 81 Vocabulary ............................................................................................................................... 81 ISA IMPLEMENTATION STANDARD.......................................................................................... 82 SMSC DS – FDC37N869 Page 5 Rev. 11/09/2000 5 Page TQFP PIN # 77 79,89 NAME Transmit Data 1 nRequest to Send (System Option) SYMBOL TXD1 nRTS1 nRTS2 (SYSOPT) 81,91 nData Terminal Ready nDTR1 nDTR2 80,90 nClear to Send nCTS1 nCTS2 78,88 nData Set Ready nDSR1 nDSR2 83,85 nData Carrier Detect nDCD1 nDCD2 BUFFER MODE6 O12 DESCRIPTION Transmit serial data output for port 1. O6 Active low Request to Send outputs for the Serial Port. Handshake output signal notifies modem that the UART is ready to transmit data. This signal can be programmed by writing to bit 1 of the Modem Control Register (MCR). The hardware reset will reset the nRTS signal to inactive mode (high). nRTS is forced inactive during loop mode operation. At the trailing edge of hardware reset the nRTS2 inputs is latched to determine the configuration base address: 0 = INDEX Base I/O Address 3F0 Hex; 1 = INDEX Base I/O Address 370 Hex. O6 Active low Data Terminal Ready outputs for the serial port. Handshake output signal notifies modem that the UART is ready to establish data communication link. This signal can be programmed by writing to bit 0 of Modem Control Register (MCR). The hardware reset will reset the nDTR signal to inactive mode (high). nDTR is forced inactive during loop mode operation. I Active low Clear to Send inputs for the serial port. Handshake signal which notifies the UART that the modem is ready to receive data. The CPU can monitor the status of nCTS signal by reading bit 4 of Modem Status Register (MSR). A nCTS signal state change from low to high after the last MSR read will set MSR bit 0 to a 1. If bit 3 of the Interrupt Enable Register is set, the interrupt is generated when nCTS changes state. The nCTS signal has no effect on the transmitter. Note: Bit 4 of MSR is the complement of nCTS. I Active low Data Set Ready inputs for the serial port. Handshake signal which notifies the UART that the modem is ready to establish the communication link. The CPU can monitor the status of nDSR signal by reading bit 5 of Modem Status Register (MSR). A nDSR signal state change from low to high after the last MSR read will set MSR bit 1 to a 1. If bit 3 of Interrupt Enable Register is set, the interrupt is generated when nDSR changes state. Note: Bit 5 of MSR is the complement of nDSR. I Active low Data Carrier Detect inputs for the serial port. Handshake signal which notifies the UART that carrier signal is detected by the modem. The CPU can monitor the status of nDCD signal by reading bit 7 of Modem Status Register (MSR). A nDCD signal state change from low to high after the last MSR read will set MSR bit 3 to a 1. If bit 3 of Interrupt Enable Register is set, the interrupt is generated when nDCD changes state. Note: Bit 7 of MSR is the complement of nDCD. SMSC DS – FDC37N869 Page 11 Rev. 11/09/2000 11 Page

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